1/* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/bl_common.ld.h> 8#include <lib/xlat_tables/xlat_tables_defs.h> 9 10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12ENTRY(bl31_entrypoint) 13 14 15MEMORY { 16 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE 17#if SEPARATE_NOBITS_REGION 18 NOBITS (rw!a): ORIGIN = BL31_NOBITS_BASE, LENGTH = BL31_NOBITS_LIMIT - BL31_NOBITS_BASE 19#else 20#define NOBITS RAM 21#endif 22} 23 24#ifdef PLAT_EXTRA_LD_SCRIPT 25#include <plat.ld.S> 26#endif 27 28SECTIONS 29{ 30 . = BL31_BASE; 31 ASSERT(. == ALIGN(PAGE_SIZE), 32 "BL31_BASE address is not aligned on a page boundary.") 33 34 __BL31_START__ = .; 35 36#if SEPARATE_CODE_AND_RODATA 37 .text . : { 38 __TEXT_START__ = .; 39 *bl31_entrypoint.o(.text*) 40 *(SORT_BY_ALIGNMENT(.text*)) 41 *(.vectors) 42 . = ALIGN(PAGE_SIZE); 43 __TEXT_END__ = .; 44 } >RAM 45 46 .rodata . : { 47 __RODATA_START__ = .; 48 *(SORT_BY_ALIGNMENT(.rodata*)) 49 50 RODATA_COMMON 51 52 /* Place pubsub sections for events */ 53 . = ALIGN(8); 54#include <lib/el3_runtime/pubsub_events.h> 55 56 . = ALIGN(PAGE_SIZE); 57 __RODATA_END__ = .; 58 } >RAM 59#else 60 ro . : { 61 __RO_START__ = .; 62 *bl31_entrypoint.o(.text*) 63 *(SORT_BY_ALIGNMENT(.text*)) 64 *(SORT_BY_ALIGNMENT(.rodata*)) 65 66 RODATA_COMMON 67 68 /* Place pubsub sections for events */ 69 . = ALIGN(8); 70#include <lib/el3_runtime/pubsub_events.h> 71 72 *(.vectors) 73 __RO_END_UNALIGNED__ = .; 74 /* 75 * Memory page(s) mapped to this section will be marked as read-only, 76 * executable. No RW data from the next section must creep in. 77 * Ensure the rest of the current memory page is unused. 78 */ 79 . = ALIGN(PAGE_SIZE); 80 __RO_END__ = .; 81 } >RAM 82#endif 83 84 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 85 "cpu_ops not defined for this platform.") 86 87#if SPM_MM 88#ifndef SPM_SHIM_EXCEPTIONS_VMA 89#define SPM_SHIM_EXCEPTIONS_VMA RAM 90#endif 91 92 /* 93 * Exception vectors of the SPM shim layer. They must be aligned to a 2K 94 * address, but we need to place them in a separate page so that we can set 95 * individual permissions to them, so the actual alignment needed is 4K. 96 * 97 * There's no need to include this into the RO section of BL31 because it 98 * doesn't need to be accessed by BL31. 99 */ 100 spm_shim_exceptions : ALIGN(PAGE_SIZE) { 101 __SPM_SHIM_EXCEPTIONS_START__ = .; 102 *(.spm_shim_exceptions) 103 . = ALIGN(PAGE_SIZE); 104 __SPM_SHIM_EXCEPTIONS_END__ = .; 105 } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM 106 107 PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions)); 108 . = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions); 109#endif 110 111 /* 112 * Define a linker symbol to mark start of the RW memory area for this 113 * image. 114 */ 115 __RW_START__ = . ; 116 117 DATA_SECTION >RAM 118 119 /* 120 * .rela.dyn needs to come after .data for the read-elf utility to parse 121 * this section correctly. Ensure 8-byte alignment so that the fields of 122 * RELA data structure are aligned. 123 */ 124 . = ALIGN(8); 125 __RELA_START__ = .; 126 .rela.dyn . : { 127 } >RAM 128 __RELA_END__ = .; 129 130#ifdef BL31_PROGBITS_LIMIT 131 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") 132#endif 133 134#if SEPARATE_NOBITS_REGION 135 /* 136 * Define a linker symbol to mark end of the RW memory area for this 137 * image. 138 */ 139 . = ALIGN(PAGE_SIZE); 140 __RW_END__ = .; 141 __BL31_END__ = .; 142 143 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") 144 145 . = BL31_NOBITS_BASE; 146 ASSERT(. == ALIGN(PAGE_SIZE), 147 "BL31 NOBITS base address is not aligned on a page boundary.") 148 149 __NOBITS_START__ = .; 150#endif 151 152 STACK_SECTION >NOBITS 153 BSS_SECTION >NOBITS 154 XLAT_TABLE_SECTION >NOBITS 155 156#if USE_COHERENT_MEM 157 /* 158 * The base address of the coherent memory section must be page-aligned (4K) 159 * to guarantee that the coherent data are stored on their own pages and 160 * are not mixed with normal data. This is required to set up the correct 161 * memory attributes for the coherent data page tables. 162 */ 163 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 164 __COHERENT_RAM_START__ = .; 165 /* 166 * Bakery locks are stored in coherent memory 167 * 168 * Each lock's data is contiguous and fully allocated by the compiler 169 */ 170 *(bakery_lock) 171 *(tzfw_coherent_mem) 172 __COHERENT_RAM_END_UNALIGNED__ = .; 173 /* 174 * Memory page(s) mapped to this section will be marked 175 * as device memory. No other unexpected data must creep in. 176 * Ensure the rest of the current memory page is unused. 177 */ 178 . = ALIGN(PAGE_SIZE); 179 __COHERENT_RAM_END__ = .; 180 } >NOBITS 181#endif 182 183#if SEPARATE_NOBITS_REGION 184 /* 185 * Define a linker symbol to mark end of the NOBITS memory area for this 186 * image. 187 */ 188 __NOBITS_END__ = .; 189 190 ASSERT(. <= BL31_NOBITS_LIMIT, "BL31 NOBITS region has exceeded its limit.") 191#else 192 /* 193 * Define a linker symbol to mark end of the RW memory area for this 194 * image. 195 */ 196 __RW_END__ = .; 197 __BL31_END__ = .; 198 199 /DISCARD/ : { 200 *(.dynsym .dynstr .hash .gnu.hash) 201 } 202 203 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") 204#endif 205} 206