1/* 2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_n3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse-N3 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_func_start neoverse_n3 25 /* Disable speculative loads */ 26 msr SSBS, xzr 27cpu_reset_func_end neoverse_n3 28 29 /* ---------------------------------------------------- 30 * HW will do the cache maintenance while powering down 31 * ---------------------------------------------------- 32 */ 33func neoverse_n3_core_pwr_dwn 34 /* --------------------------------------------------- 35 * Enable CPU power down bit in power control register 36 * --------------------------------------------------- 37 */ 38 sysreg_bit_set NEOVERSE_N3_CPUPWRCTLR_EL1, NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 39 isb 40 ret 41endfunc neoverse_n3_core_pwr_dwn 42 43errata_report_shim neoverse_n3 44 45 /* --------------------------------------------- 46 * This function provides Neoverse-N3 specific 47 * register information for crash reporting. 48 * It needs to return with x6 pointing to 49 * a list of register names in ascii and 50 * x8 - x15 having values of registers to be 51 * reported. 52 * --------------------------------------------- 53 */ 54.section .rodata.neoverse_n3_regs, "aS" 55neoverse_n3_regs: /* The ascii list of register names to be reported */ 56 .asciz "cpuectlr_el1", "" 57 58func neoverse_n3_cpu_reg_dump 59 adr x6, neoverse_n3_regs 60 mrs x8, NEOVERSE_N3_CPUECTLR_EL1 61 ret 62endfunc neoverse_n3_cpu_reg_dump 63 64declare_cpu_ops neoverse_n3, NEOVERSE_N3_MIDR, \ 65 neoverse_n3_reset_func, \ 66 neoverse_n3_core_pwr_dwn 67