xref: /rk3399_ARM-atf/bl32/sp_min/sp_min.ld.S (revision 04e06973e1fef87849c498c7f045aa2be8aada1c) 
1/*
2 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(elf32-littlearm)
11OUTPUT_ARCH(arm)
12ENTRY(sp_min_vector_table)
13
14MEMORY {
15    RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE
16}
17
18#ifdef PLAT_SP_MIN_EXTRA_LD_SCRIPT
19#include <plat_sp_min.ld.S>
20#endif
21
22SECTIONS
23{
24    . = BL32_BASE;
25   ASSERT(. == ALIGN(PAGE_SIZE),
26          "BL32_BASE address is not aligned on a page boundary.")
27
28#if SEPARATE_CODE_AND_RODATA
29    .text . : {
30        __TEXT_START__ = .;
31        *entrypoint.o(.text*)
32        *(.text*)
33        *(.vectors)
34        . = ALIGN(PAGE_SIZE);
35        __TEXT_END__ = .;
36    } >RAM
37
38     /* .ARM.extab and .ARM.exidx are only added because Clang need them */
39     .ARM.extab . : {
40        *(.ARM.extab* .gnu.linkonce.armextab.*)
41     } >RAM
42
43     .ARM.exidx . : {
44        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
45     } >RAM
46
47    .rodata . : {
48        __RODATA_START__ = .;
49        *(.rodata*)
50
51	RODATA_COMMON
52
53        /* Place pubsub sections for events */
54        . = ALIGN(8);
55#include <lib/el3_runtime/pubsub_events.h>
56
57        . = ALIGN(PAGE_SIZE);
58        __RODATA_END__ = .;
59    } >RAM
60#else
61    ro . : {
62        __RO_START__ = .;
63        *entrypoint.o(.text*)
64        *(.text*)
65        *(.rodata*)
66
67	RODATA_COMMON
68
69        /* Place pubsub sections for events */
70        . = ALIGN(8);
71#include <lib/el3_runtime/pubsub_events.h>
72
73        *(.vectors)
74        __RO_END_UNALIGNED__ = .;
75
76        /*
77         * Memory page(s) mapped to this section will be marked as
78         * read-only, executable.  No RW data from the next section must
79         * creep in.  Ensure the rest of the current memory block is unused.
80         */
81        . = ALIGN(PAGE_SIZE);
82        __RO_END__ = .;
83    } >RAM
84#endif
85
86    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
87           "cpu_ops not defined for this platform.")
88    /*
89     * Define a linker symbol to mark start of the RW memory area for this
90     * image.
91     */
92    __RW_START__ = . ;
93
94    DATA_SECTION >RAM
95
96#ifdef BL32_PROGBITS_LIMIT
97    ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.")
98#endif
99
100    STACK_SECTION >RAM
101    BSS_SECTION >RAM
102    XLAT_TABLE_SECTION >RAM
103
104     __BSS_SIZE__ = SIZEOF(.bss);
105
106#if USE_COHERENT_MEM
107    /*
108     * The base address of the coherent memory section must be page-aligned (4K)
109     * to guarantee that the coherent data are stored on their own pages and
110     * are not mixed with normal data.  This is required to set up the correct
111     * memory attributes for the coherent data page tables.
112     */
113    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
114        __COHERENT_RAM_START__ = .;
115        /*
116         * Bakery locks are stored in coherent memory
117         *
118         * Each lock's data is contiguous and fully allocated by the compiler
119         */
120        *(bakery_lock)
121        *(tzfw_coherent_mem)
122        __COHERENT_RAM_END_UNALIGNED__ = .;
123        /*
124         * Memory page(s) mapped to this section will be marked
125         * as device memory.  No other unexpected data must creep in.
126         * Ensure the rest of the current memory page is unused.
127         */
128        . = ALIGN(PAGE_SIZE);
129        __COHERENT_RAM_END__ = .;
130    } >RAM
131
132    __COHERENT_RAM_UNALIGNED_SIZE__ =
133        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
134#endif
135
136    /*
137     * Define a linker symbol to mark end of the RW memory area for this
138     * image.
139     */
140    __RW_END__ = .;
141
142   __BL32_END__ = .;
143}
144