1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef TEGRA_PRIVATE_H 9 #define TEGRA_PRIVATE_H 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <drivers/ti/uart/uart_16550.h> 16 #include <lib/psci/psci.h> 17 #include <lib/xlat_tables/xlat_tables_v2.h> 18 19 #include <tegra_gic.h> 20 21 /******************************************************************************* 22 * Implementation defined ACTLR_EL1 bit definitions 23 ******************************************************************************/ 24 #define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0) 25 26 /******************************************************************************* 27 * Implementation defined ACTLR_EL2 bit definitions 28 ******************************************************************************/ 29 #define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0) 30 31 /******************************************************************************* 32 * Struct for parameters received from BL2 33 ******************************************************************************/ 34 typedef struct plat_params_from_bl2 { 35 /* TZ memory size */ 36 uint64_t tzdram_size; 37 /* TZ memory base */ 38 uint64_t tzdram_base; 39 /* UART port ID */ 40 int32_t uart_id; 41 /* L2 ECC parity protection disable flag */ 42 int32_t l2_ecc_parity_prot_dis; 43 /* SHMEM base address for storing the boot logs */ 44 uint64_t boot_profiler_shmem_base; 45 /* System Suspend Entry Firmware size */ 46 uint64_t sc7entry_fw_size; 47 /* System Suspend Entry Firmware base address */ 48 uint64_t sc7entry_fw_base; 49 } plat_params_from_bl2_t; 50 51 /******************************************************************************* 52 * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs 53 ******************************************************************************/ 54 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 55 56 /******************************************************************************* 57 * Struct describing parameters passed to bl31 58 ******************************************************************************/ 59 struct tegra_bl31_params { 60 param_header_t h; 61 image_info_t *bl31_image_info; 62 entry_point_info_t *bl32_ep_info; 63 image_info_t *bl32_image_info; 64 entry_point_info_t *bl33_ep_info; 65 image_info_t *bl33_image_info; 66 }; 67 68 /* Declarations for plat_psci_handlers.c */ 69 int32_t tegra_soc_validate_power_state(uint32_t power_state, 70 psci_power_state_t *req_state); 71 72 /* Declarations for plat_setup.c */ 73 const mmap_region_t *plat_get_mmio_map(void); 74 void plat_enable_console(int32_t id); 75 void plat_gic_setup(void); 76 struct tegra_bl31_params *plat_get_bl31_params(void); 77 plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 78 void plat_early_platform_setup(void); 79 void plat_late_platform_setup(void); 80 81 /* Declarations for plat_secondary.c */ 82 void plat_secondary_setup(void); 83 int32_t plat_lock_cpu_vectors(void); 84 85 /* Declarations for tegra_fiq_glue.c */ 86 void tegra_fiq_handler_setup(void); 87 int tegra_fiq_get_intr_context(void); 88 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 89 90 /* Declarations for tegra_security.c */ 91 void tegra_security_setup(void); 92 void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 93 94 /* Declarations for tegra_pm.c */ 95 void tegra_pm_system_suspend_entry(void); 96 void tegra_pm_system_suspend_exit(void); 97 int32_t tegra_system_suspended(void); 98 int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state); 99 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state); 100 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); 101 int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); 102 int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state); 103 int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 104 int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state); 105 int32_t tegra_soc_prepare_system_reset(void); 106 __dead2 void tegra_soc_prepare_system_off(void); 107 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, 108 const plat_local_state_t *states, 109 uint32_t ncpu); 110 void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state); 111 void tegra_cpu_standby(plat_local_state_t cpu_state); 112 int32_t tegra_pwr_domain_on(u_register_t mpidr); 113 void tegra_pwr_domain_off(const psci_power_state_t *target_state); 114 void tegra_pwr_domain_suspend(const psci_power_state_t *target_state); 115 void __dead2 tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 116 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state); 117 void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state); 118 __dead2 void tegra_system_off(void); 119 __dead2 void tegra_system_reset(void); 120 int32_t tegra_validate_power_state(uint32_t power_state, 121 psci_power_state_t *req_state); 122 int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint); 123 124 /* Declarations for tegraXXX_pm.c */ 125 int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 126 int tegra_prepare_cpu_on_finish(unsigned long mpidr); 127 128 /* Declarations for tegra_bl31_setup.c */ 129 plat_params_from_bl2_t *bl31_get_plat_params(void); 130 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 131 132 /* Declarations for tegra_delay_timer.c */ 133 void tegra_delay_timer_init(void); 134 135 void tegra_secure_entrypoint(void); 136 137 /* Declarations for tegra_sip_calls.c */ 138 uintptr_t tegra_sip_handler(uint32_t smc_fid, 139 u_register_t x1, 140 u_register_t x2, 141 u_register_t x3, 142 u_register_t x4, 143 void *cookie, 144 void *handle, 145 u_register_t flags); 146 int plat_sip_handler(uint32_t smc_fid, 147 uint64_t x1, 148 uint64_t x2, 149 uint64_t x3, 150 uint64_t x4, 151 const void *cookie, 152 void *handle, 153 uint64_t flags); 154 155 #endif /* TEGRA_PRIVATE_H */ 156