1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/arm/css/css_scp.h> 15 #include <lib/cassert.h> 16 #include <plat/arm/common/plat_arm.h> 17 #include <plat/arm/css/common/css_pm.h> 18 #include <plat/common/platform.h> 19 20 /* Allow CSS platforms to override `plat_arm_psci_pm_ops` */ 21 #pragma weak plat_arm_psci_pm_ops 22 23 #if ARM_RECOM_STATE_ID_ENC 24 /* 25 * The table storing the valid idle power states. Ensure that the 26 * array entries are populated in ascending order of state-id to 27 * enable us to use binary search during power state validation. 28 * The table must be terminated by a NULL entry. 29 */ 30 const unsigned int arm_pm_idle_states[] = { 31 /* State-id - 0x001 */ 32 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 33 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 34 /* State-id - 0x002 */ 35 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 36 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 37 /* State-id - 0x022 */ 38 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 39 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 40 #if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1 41 /* State-id - 0x222 */ 42 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 43 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), 44 #endif 45 0, 46 }; 47 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 48 49 /* 50 * All the power management helpers in this file assume at least cluster power 51 * level is supported. 52 */ 53 CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1, 54 assert_max_pwr_lvl_supported_mismatch); 55 56 /* 57 * Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL 58 * assumed by the CSS layer. 59 */ 60 CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL, 61 assert_max_pwr_lvl_higher_than_css_sys_lvl); 62 63 /******************************************************************************* 64 * Handler called when a power domain is about to be turned on. The 65 * level and mpidr determine the affinity instance. 66 ******************************************************************************/ 67 int css_pwr_domain_on(u_register_t mpidr) 68 { 69 css_scp_on(mpidr); 70 71 return PSCI_E_SUCCESS; 72 } 73 74 static void css_pwr_domain_on_finisher_common( 75 const psci_power_state_t *target_state) 76 { 77 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 78 79 /* Enable the gic cpu interface */ 80 plat_arm_gic_cpuif_enable(); 81 82 /* 83 * Perform the common cluster specific operations i.e enable coherency 84 * if this cluster was off. 85 */ 86 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) 87 plat_arm_interconnect_enter_coherency(); 88 } 89 90 /******************************************************************************* 91 * Handler called when a power level has just been powered on after 92 * being turned off earlier. The target_state encodes the low power state that 93 * each level has woken up from. This handler would never be invoked with 94 * the system power domain uninitialized as either the primary would have taken 95 * care of it as part of cold boot or the first core awakened from system 96 * suspend would have already initialized it. 97 ******************************************************************************/ 98 void css_pwr_domain_on_finish(const psci_power_state_t *target_state) 99 { 100 /* Assert that the system power domain need not be initialized */ 101 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); 102 103 /* Program the gic per-cpu distributor or re-distributor interface */ 104 plat_arm_gic_pcpu_init(); 105 106 css_pwr_domain_on_finisher_common(target_state); 107 } 108 109 /******************************************************************************* 110 * Common function called while turning a cpu off or suspending it. It is called 111 * from css_off() or css_suspend() when these functions in turn are called for 112 * power domain at the highest power level which will be powered down. It 113 * performs the actions common to the OFF and SUSPEND calls. 114 ******************************************************************************/ 115 static void css_power_down_common(const psci_power_state_t *target_state) 116 { 117 /* Prevent interrupts from spuriously waking up this cpu */ 118 plat_arm_gic_cpuif_disable(); 119 120 /* Cluster is to be turned off, so disable coherency */ 121 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) 122 plat_arm_interconnect_exit_coherency(); 123 } 124 125 /******************************************************************************* 126 * Handler called when a power domain is about to be turned off. The 127 * target_state encodes the power state that each level should transition to. 128 ******************************************************************************/ 129 void css_pwr_domain_off(const psci_power_state_t *target_state) 130 { 131 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 132 css_power_down_common(target_state); 133 css_scp_off(target_state); 134 } 135 136 /******************************************************************************* 137 * Handler called when a power domain is about to be suspended. The 138 * target_state encodes the power state that each level should transition to. 139 ******************************************************************************/ 140 void css_pwr_domain_suspend(const psci_power_state_t *target_state) 141 { 142 /* 143 * CSS currently supports retention only at cpu level. Just return 144 * as nothing is to be done for retention. 145 */ 146 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 147 return; 148 149 150 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 151 css_power_down_common(target_state); 152 153 /* Perform system domain state saving if issuing system suspend */ 154 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) { 155 arm_system_pwr_domain_save(); 156 157 /* Power off the Redistributor after having saved its context */ 158 plat_arm_gic_redistif_off(); 159 } 160 161 css_scp_suspend(target_state); 162 } 163 164 /******************************************************************************* 165 * Handler called when a power domain has just been powered on after 166 * having been suspended earlier. The target_state encodes the low power state 167 * that each level has woken up from. 168 * TODO: At the moment we reuse the on finisher and reinitialize the secure 169 * context. Need to implement a separate suspend finisher. 170 ******************************************************************************/ 171 void css_pwr_domain_suspend_finish( 172 const psci_power_state_t *target_state) 173 { 174 /* Return as nothing is to be done on waking up from retention. */ 175 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 176 return; 177 178 /* Perform system domain restore if woken up from system suspend */ 179 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) 180 /* 181 * At this point, the Distributor must be powered on to be ready 182 * to have its state restored. The Redistributor will be powered 183 * on as part of gicv3_rdistif_init_restore. 184 */ 185 arm_system_pwr_domain_resume(); 186 187 css_pwr_domain_on_finisher_common(target_state); 188 } 189 190 /******************************************************************************* 191 * Handlers to shutdown/reboot the system 192 ******************************************************************************/ 193 void __dead2 css_system_off(void) 194 { 195 css_scp_sys_shutdown(); 196 } 197 198 void __dead2 css_system_reset(void) 199 { 200 css_scp_sys_reboot(); 201 } 202 203 /******************************************************************************* 204 * Handler called when the CPU power domain is about to enter standby. 205 ******************************************************************************/ 206 void css_cpu_standby(plat_local_state_t cpu_state) 207 { 208 unsigned int scr; 209 210 assert(cpu_state == ARM_LOCAL_STATE_RET); 211 212 scr = read_scr_el3(); 213 /* 214 * Enable the Non secure interrupt to wake the CPU. 215 * In GICv3 affinity routing mode, the non secure group1 interrupts use 216 * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ. 217 * Enabling both the bits works for both GICv2 mode and GICv3 affinity 218 * routing mode. 219 */ 220 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 221 isb(); 222 dsb(); 223 wfi(); 224 225 /* 226 * Restore SCR to the original value, synchronisation of scr_el3 is 227 * done by eret while el3_exit to save some execution cycles. 228 */ 229 write_scr_el3(scr); 230 } 231 232 /******************************************************************************* 233 * Handler called to return the 'req_state' for system suspend. 234 ******************************************************************************/ 235 void css_get_sys_suspend_power_state(psci_power_state_t *req_state) 236 { 237 unsigned int i; 238 239 /* 240 * System Suspend is supported only if the system power domain node 241 * is implemented. 242 */ 243 assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL); 244 245 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 246 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 247 } 248 249 /******************************************************************************* 250 * Handler to query CPU/cluster power states from SCP 251 ******************************************************************************/ 252 int css_node_hw_state(u_register_t mpidr, unsigned int power_level) 253 { 254 return css_scp_get_power_state(mpidr, power_level); 255 } 256 257 /* 258 * The system power domain suspend is only supported only via 259 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain 260 * will be downgraded to the lower level. 261 */ 262 static int css_validate_power_state(unsigned int power_state, 263 psci_power_state_t *req_state) 264 { 265 int rc; 266 rc = arm_validate_power_state(power_state, req_state); 267 268 /* 269 * Ensure that we don't overrun the pwr_domain_state array in the case 270 * where the platform supported max power level is less than the system 271 * power level 272 */ 273 274 #if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) 275 276 /* 277 * Ensure that the system power domain level is never suspended 278 * via PSCI CPU SUSPEND API. Currently system suspend is only 279 * supported via PSCI SYSTEM SUSPEND API. 280 */ 281 282 req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = 283 ARM_LOCAL_STATE_RUN; 284 #endif 285 286 return rc; 287 } 288 289 /* 290 * Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the 291 * `css_validate_power_state`, we do not downgrade the system power 292 * domain level request in `power_state` as it will be used to query the 293 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. 294 */ 295 static int css_translate_power_state_by_mpidr(u_register_t mpidr, 296 unsigned int power_state, 297 psci_power_state_t *output_state) 298 { 299 return arm_validate_power_state(power_state, output_state); 300 } 301 302 /******************************************************************************* 303 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 304 * platform will take care of registering the handlers with PSCI. 305 ******************************************************************************/ 306 plat_psci_ops_t plat_arm_psci_pm_ops = { 307 .pwr_domain_on = css_pwr_domain_on, 308 .pwr_domain_on_finish = css_pwr_domain_on_finish, 309 .pwr_domain_off = css_pwr_domain_off, 310 .cpu_standby = css_cpu_standby, 311 .pwr_domain_suspend = css_pwr_domain_suspend, 312 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish, 313 .system_off = css_system_off, 314 .system_reset = css_system_reset, 315 .validate_power_state = css_validate_power_state, 316 .validate_ns_entrypoint = arm_validate_psci_entrypoint, 317 .translate_power_state_by_mpidr = css_translate_power_state_by_mpidr, 318 .get_node_hw_state = css_node_hw_state, 319 .get_sys_suspend_power_state = css_get_sys_suspend_power_state, 320 321 #if defined(PLAT_ARM_MEM_PROT_ADDR) 322 .mem_protect_chk = arm_psci_mem_protect_chk, 323 .read_mem_protect = arm_psci_read_mem_protect, 324 .write_mem_protect = arm_nor_psci_write_mem_protect, 325 #endif 326 #if CSS_USE_SCMI_SDS_DRIVER 327 .system_reset2 = css_system_reset2, 328 #endif 329 }; 330