1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <context.h> 15 #include <drivers/console.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 #include <lib/mmio.h> 18 #include <lib/psci/psci.h> 19 #include <plat/common/platform.h> 20 21 #include <memctrl.h> 22 #include <pmc.h> 23 #include <tegra_def.h> 24 #include <tegra_platform.h> 25 #include <tegra_private.h> 26 27 extern uint64_t tegra_bl31_phys_base; 28 extern uint64_t tegra_sec_entry_point; 29 extern uint64_t tegra_console_base; 30 31 /* 32 * tegra_fake_system_suspend acts as a boolean var controlling whether 33 * we are going to take fake system suspend code or normal system suspend code 34 * path. This variable is set inside the sip call handlers,when the kernel 35 * requests a SIP call to set the suspend debug flags. 36 */ 37 uint8_t tegra_fake_system_suspend; 38 39 /* 40 * The following platform setup functions are weakly defined. They 41 * provide typical implementations that will be overridden by a SoC. 42 */ 43 #pragma weak tegra_soc_pwr_domain_suspend_pwrdown_early 44 #pragma weak tegra_soc_pwr_domain_suspend 45 #pragma weak tegra_soc_pwr_domain_on 46 #pragma weak tegra_soc_pwr_domain_off 47 #pragma weak tegra_soc_pwr_domain_on_finish 48 #pragma weak tegra_soc_pwr_domain_power_down_wfi 49 #pragma weak tegra_soc_prepare_system_reset 50 #pragma weak tegra_soc_prepare_system_off 51 #pragma weak tegra_soc_get_target_pwr_state 52 53 int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) 54 { 55 return PSCI_E_NOT_SUPPORTED; 56 } 57 58 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 59 { 60 (void)target_state; 61 return PSCI_E_NOT_SUPPORTED; 62 } 63 64 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) 65 { 66 (void)mpidr; 67 return PSCI_E_SUCCESS; 68 } 69 70 int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 71 { 72 (void)target_state; 73 return PSCI_E_SUCCESS; 74 } 75 76 int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 77 { 78 (void)target_state; 79 return PSCI_E_SUCCESS; 80 } 81 82 int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 83 { 84 (void)target_state; 85 return PSCI_E_SUCCESS; 86 } 87 88 int32_t tegra_soc_prepare_system_reset(void) 89 { 90 return PSCI_E_SUCCESS; 91 } 92 93 __dead2 void tegra_soc_prepare_system_off(void) 94 { 95 ERROR("Tegra System Off: operation not handled.\n"); 96 panic(); 97 } 98 99 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, 100 const plat_local_state_t *states, 101 uint32_t ncpu) 102 { 103 plat_local_state_t target = PLAT_MAX_OFF_STATE, temp; 104 uint32_t num_cpu = ncpu; 105 const plat_local_state_t *local_state = states; 106 107 (void)lvl; 108 109 assert(ncpu != 0U); 110 111 do { 112 temp = *local_state; 113 if ((temp < target)) { 114 target = temp; 115 } 116 --num_cpu; 117 local_state++; 118 } while (num_cpu != 0U); 119 120 return target; 121 } 122 123 /******************************************************************************* 124 * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` 125 * call to get the `power_state` parameter. This allows the platform to encode 126 * the appropriate State-ID field within the `power_state` parameter which can 127 * be utilized in `pwr_domain_suspend()` to suspend to system affinity level. 128 ******************************************************************************/ 129 void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state) 130 { 131 /* all affinities use system suspend state id */ 132 for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { 133 req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN; 134 } 135 } 136 137 /******************************************************************************* 138 * Handler called when an affinity instance is about to enter standby. 139 ******************************************************************************/ 140 void tegra_cpu_standby(plat_local_state_t cpu_state) 141 { 142 (void)cpu_state; 143 144 /* 145 * Enter standby state 146 * dsb is good practice before using wfi to enter low power states 147 */ 148 dsb(); 149 wfi(); 150 } 151 152 /******************************************************************************* 153 * Handler called when an affinity instance is about to be turned on. The 154 * level and mpidr determine the affinity instance. 155 ******************************************************************************/ 156 int32_t tegra_pwr_domain_on(u_register_t mpidr) 157 { 158 return tegra_soc_pwr_domain_on(mpidr); 159 } 160 161 /******************************************************************************* 162 * Handler called when a power domain is about to be turned off. The 163 * target_state encodes the power state that each level should transition to. 164 ******************************************************************************/ 165 void tegra_pwr_domain_off(const psci_power_state_t *target_state) 166 { 167 (void)tegra_soc_pwr_domain_off(target_state); 168 } 169 170 /******************************************************************************* 171 * Handler called when a power domain is about to be suspended. The 172 * target_state encodes the power state that each level should transition to. 173 * This handler is called with SMP and data cache enabled, when 174 * HW_ASSISTED_COHERENCY = 0 175 ******************************************************************************/ 176 void tegra_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) 177 { 178 tegra_soc_pwr_domain_suspend_pwrdown_early(target_state); 179 } 180 181 /******************************************************************************* 182 * Handler called when a power domain is about to be suspended. The 183 * target_state encodes the power state that each level should transition to. 184 ******************************************************************************/ 185 void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) 186 { 187 (void)tegra_soc_pwr_domain_suspend(target_state); 188 189 /* Disable console if we are entering deep sleep. */ 190 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 191 PSTATE_ID_SOC_POWERDN) { 192 (void)console_uninit(); 193 } 194 195 /* disable GICC */ 196 tegra_gic_cpuif_deactivate(); 197 } 198 199 /******************************************************************************* 200 * Handler called at the end of the power domain suspend sequence. The 201 * target_state encodes the power state that each level should transition to. 202 ******************************************************************************/ 203 __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t 204 *target_state) 205 { 206 uint8_t pwr_state = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; 207 uint64_t rmr_el3 = 0; 208 209 /* call the chip's power down handler */ 210 (void)tegra_soc_pwr_domain_power_down_wfi(target_state); 211 212 /* 213 * If we are in fake system suspend mode, ensure we start doing 214 * procedures that help in looping back towards system suspend exit 215 * instead of calling WFI by requesting a warm reset. 216 * Else, just call WFI to enter low power state. 217 */ 218 if ((tegra_fake_system_suspend != 0U) && 219 (pwr_state == (uint8_t)PSTATE_ID_SOC_POWERDN)) { 220 221 /* warm reboot */ 222 rmr_el3 = read_rmr_el3(); 223 write_rmr_el3(rmr_el3 | RMR_WARM_RESET_CPU); 224 225 } else { 226 /* enter power down state */ 227 wfi(); 228 } 229 230 /* we can never reach here */ 231 panic(); 232 } 233 234 /******************************************************************************* 235 * Handler called when a power domain has just been powered on after 236 * being turned off earlier. The target_state encodes the low power state that 237 * each level has woken up from. 238 ******************************************************************************/ 239 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) 240 { 241 const plat_params_from_bl2_t *plat_params; 242 uint32_t console_clock; 243 244 /* 245 * Initialize the GIC cpu and distributor interfaces 246 */ 247 plat_gic_setup(); 248 249 /* 250 * Check if we are exiting from deep sleep. 251 */ 252 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 253 PSTATE_ID_SOC_POWERDN) { 254 255 /* 256 * Reference clock used by the FPGAs is a lot slower. 257 */ 258 if (tegra_platform_is_fpga()) { 259 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; 260 } else { 261 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; 262 } 263 264 /* Initialize the runtime console */ 265 if (tegra_console_base != 0ULL) { 266 (void)console_init(tegra_console_base, console_clock, 267 TEGRA_CONSOLE_BAUDRATE); 268 } 269 270 /* 271 * Restore Memory Controller settings as it loses state 272 * during system suspend. 273 */ 274 tegra_memctrl_restore_settings(); 275 276 /* 277 * Security configuration to allow DRAM/device access. 278 */ 279 plat_params = bl31_get_plat_params(); 280 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, 281 (uint32_t)plat_params->tzdram_size); 282 283 /* 284 * Set up the TZRAM memory aperture to allow only secure world 285 * access 286 */ 287 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 288 } 289 290 /* 291 * Reset hardware settings. 292 */ 293 (void)tegra_soc_pwr_domain_on_finish(target_state); 294 } 295 296 /******************************************************************************* 297 * Handler called when a power domain has just been powered on after 298 * having been suspended earlier. The target_state encodes the low power state 299 * that each level has woken up from. 300 ******************************************************************************/ 301 void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 302 { 303 tegra_pwr_domain_on_finish(target_state); 304 } 305 306 /******************************************************************************* 307 * Handler called when the system wants to be powered off 308 ******************************************************************************/ 309 __dead2 void tegra_system_off(void) 310 { 311 INFO("Powering down system...\n"); 312 313 tegra_soc_prepare_system_off(); 314 } 315 316 /******************************************************************************* 317 * Handler called when the system wants to be restarted. 318 ******************************************************************************/ 319 __dead2 void tegra_system_reset(void) 320 { 321 INFO("Restarting system...\n"); 322 323 /* per-SoC system reset handler */ 324 (void)tegra_soc_prepare_system_reset(); 325 326 /* 327 * Program the PMC in order to restart the system. 328 */ 329 tegra_pmc_system_reset(); 330 } 331 332 /******************************************************************************* 333 * Handler called to check the validity of the power state parameter. 334 ******************************************************************************/ 335 int32_t tegra_validate_power_state(uint32_t power_state, 336 psci_power_state_t *req_state) 337 { 338 assert(req_state != NULL); 339 340 return tegra_soc_validate_power_state(power_state, req_state); 341 } 342 343 /******************************************************************************* 344 * Platform handler called to check the validity of the non secure entrypoint. 345 ******************************************************************************/ 346 int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint) 347 { 348 int32_t ret = PSCI_E_INVALID_ADDRESS; 349 350 /* 351 * Check if the non secure entrypoint lies within the non 352 * secure DRAM. 353 */ 354 if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) { 355 ret = PSCI_E_SUCCESS; 356 } 357 358 return ret; 359 } 360 361 /******************************************************************************* 362 * Export the platform handlers to enable psci to invoke them 363 ******************************************************************************/ 364 static const plat_psci_ops_t tegra_plat_psci_ops = { 365 .cpu_standby = tegra_cpu_standby, 366 .pwr_domain_on = tegra_pwr_domain_on, 367 .pwr_domain_off = tegra_pwr_domain_off, 368 .pwr_domain_suspend_pwrdown_early = tegra_pwr_domain_suspend_pwrdown_early, 369 .pwr_domain_suspend = tegra_pwr_domain_suspend, 370 .pwr_domain_on_finish = tegra_pwr_domain_on_finish, 371 .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, 372 .pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi, 373 .system_off = tegra_system_off, 374 .system_reset = tegra_system_reset, 375 .validate_power_state = tegra_validate_power_state, 376 .validate_ns_entrypoint = tegra_validate_ns_entrypoint, 377 .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state, 378 }; 379 380 /******************************************************************************* 381 * Export the platform specific power ops and initialize Power Controller 382 ******************************************************************************/ 383 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 384 const plat_psci_ops_t **psci_ops) 385 { 386 psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } }; 387 388 /* 389 * Flush entrypoint variable to PoC since it will be 390 * accessed after a reset with the caches turned off. 391 */ 392 tegra_sec_entry_point = sec_entrypoint; 393 flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t)); 394 395 /* 396 * Reset hardware settings. 397 */ 398 (void)tegra_soc_pwr_domain_on_finish(&target_state); 399 400 /* 401 * Initialize PSCI ops struct 402 */ 403 *psci_ops = &tegra_plat_psci_ops; 404 405 return 0; 406 } 407 408 /******************************************************************************* 409 * Platform handler to calculate the proper target power level at the 410 * specified affinity level 411 ******************************************************************************/ 412 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, 413 const plat_local_state_t *states, 414 unsigned int ncpu) 415 { 416 return tegra_soc_get_target_pwr_state(lvl, states, ncpu); 417 } 418