1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_H 8 #define ARCH_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(0x18) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_VAR_MASK U(0xf) 20 #define MIDR_REV_SHIFT U(0) 21 #define MIDR_REV_BITS U(4) 22 #define MIDR_REV_MASK U(0xf) 23 #define MIDR_PN_MASK U(0xfff) 24 #define MIDR_PN_SHIFT U(0x4) 25 26 /******************************************************************************* 27 * MPIDR macros 28 ******************************************************************************/ 29 #define MPIDR_MT_MASK (ULL(1) << 24) 30 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 31 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 32 #define MPIDR_AFFINITY_BITS U(8) 33 #define MPIDR_AFFLVL_MASK ULL(0xff) 34 #define MPIDR_AFF0_SHIFT U(0) 35 #define MPIDR_AFF1_SHIFT U(8) 36 #define MPIDR_AFF2_SHIFT U(16) 37 #define MPIDR_AFF3_SHIFT U(32) 38 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 39 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 40 #define MPIDR_AFFLVL_SHIFT U(3) 41 #define MPIDR_AFFLVL0 ULL(0x0) 42 #define MPIDR_AFFLVL1 ULL(0x1) 43 #define MPIDR_AFFLVL2 ULL(0x2) 44 #define MPIDR_AFFLVL3 ULL(0x3) 45 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 46 #define MPIDR_AFFLVL0_VAL(mpidr) \ 47 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 48 #define MPIDR_AFFLVL1_VAL(mpidr) \ 49 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 50 #define MPIDR_AFFLVL2_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL3_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 54 /* 55 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 56 * add one while using this macro to define array sizes. 57 * TODO: Support only the first 3 affinity levels for now. 58 */ 59 #define MPIDR_MAX_AFFLVL U(2) 60 61 #define MPID_MASK (MPIDR_MT_MASK | \ 62 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 66 67 #define MPIDR_AFF_ID(mpid, n) \ 68 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 69 70 /* 71 * An invalid MPID. This value can be used by functions that return an MPID to 72 * indicate an error. 73 */ 74 #define INVALID_MPID U(0xFFFFFFFF) 75 76 /******************************************************************************* 77 * Definitions for CPU system register interface to GICv3 78 ******************************************************************************/ 79 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 80 #define ICC_SGI1R S3_0_C12_C11_5 81 #define ICC_SRE_EL1 S3_0_C12_C12_5 82 #define ICC_SRE_EL2 S3_4_C12_C9_5 83 #define ICC_SRE_EL3 S3_6_C12_C12_5 84 #define ICC_CTLR_EL1 S3_0_C12_C12_4 85 #define ICC_CTLR_EL3 S3_6_C12_C12_4 86 #define ICC_PMR_EL1 S3_0_C4_C6_0 87 #define ICC_RPR_EL1 S3_0_C12_C11_3 88 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 89 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 90 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 91 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 92 #define ICC_IAR0_EL1 S3_0_c12_c8_0 93 #define ICC_IAR1_EL1 S3_0_c12_c12_0 94 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 95 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 96 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 97 98 /******************************************************************************* 99 * Generic timer memory mapped registers & offsets 100 ******************************************************************************/ 101 #define CNTCR_OFF U(0x000) 102 #define CNTFID_OFF U(0x020) 103 104 #define CNTCR_EN (U(1) << 0) 105 #define CNTCR_HDBG (U(1) << 1) 106 #define CNTCR_FCREQ(x) ((x) << 8) 107 108 /******************************************************************************* 109 * System register bit definitions 110 ******************************************************************************/ 111 /* CLIDR definitions */ 112 #define LOUIS_SHIFT U(21) 113 #define LOC_SHIFT U(24) 114 #define CLIDR_FIELD_WIDTH U(3) 115 116 /* CSSELR definitions */ 117 #define LEVEL_SHIFT U(1) 118 119 /* Data cache set/way op type defines */ 120 #define DCISW U(0x0) 121 #define DCCISW U(0x1) 122 #if ERRATA_A53_827319 123 #define DCCSW DCCISW 124 #else 125 #define DCCSW U(0x2) 126 #endif 127 128 /* ID_AA64PFR0_EL1 definitions */ 129 #define ID_AA64PFR0_EL0_SHIFT U(0) 130 #define ID_AA64PFR0_EL1_SHIFT U(4) 131 #define ID_AA64PFR0_EL2_SHIFT U(8) 132 #define ID_AA64PFR0_EL3_SHIFT U(12) 133 #define ID_AA64PFR0_AMU_SHIFT U(44) 134 #define ID_AA64PFR0_AMU_LENGTH U(4) 135 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 136 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 137 #define ID_AA64PFR0_SVE_SHIFT U(32) 138 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 139 #define ID_AA64PFR0_SVE_LENGTH U(4) 140 #define ID_AA64PFR0_MPAM_SHIFT U(40) 141 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 142 #define ID_AA64PFR0_DIT_SHIFT U(48) 143 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 144 #define ID_AA64PFR0_DIT_LENGTH U(4) 145 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 146 #define ID_AA64PFR0_CSV2_SHIFT U(56) 147 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 148 #define ID_AA64PFR0_CSV2_LENGTH U(4) 149 150 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 151 #define ID_AA64DFR0_PMS_SHIFT U(32) 152 #define ID_AA64DFR0_PMS_LENGTH U(4) 153 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 154 155 #define EL_IMPL_NONE ULL(0) 156 #define EL_IMPL_A64ONLY ULL(1) 157 #define EL_IMPL_A64_A32 ULL(2) 158 159 #define ID_AA64PFR0_GIC_SHIFT U(24) 160 #define ID_AA64PFR0_GIC_WIDTH U(4) 161 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 162 163 /* ID_AA64ISAR1_EL1 definitions */ 164 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 165 #define ID_AA64ISAR1_GPI_SHIFT U(28) 166 #define ID_AA64ISAR1_GPI_WIDTH U(4) 167 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 168 #define ID_AA64ISAR1_GPA_SHIFT U(24) 169 #define ID_AA64ISAR1_GPA_WIDTH U(4) 170 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 171 #define ID_AA64ISAR1_API_SHIFT U(8) 172 #define ID_AA64ISAR1_API_WIDTH U(4) 173 #define ID_AA64ISAR1_API_MASK ULL(0xf) 174 #define ID_AA64ISAR1_APA_SHIFT U(4) 175 #define ID_AA64ISAR1_APA_WIDTH U(4) 176 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 177 178 /* ID_AA64MMFR0_EL1 definitions */ 179 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 180 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 181 182 #define PARANGE_0000 U(32) 183 #define PARANGE_0001 U(36) 184 #define PARANGE_0010 U(40) 185 #define PARANGE_0011 U(42) 186 #define PARANGE_0100 U(44) 187 #define PARANGE_0101 U(48) 188 #define PARANGE_0110 U(52) 189 190 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 191 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 192 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 193 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 194 195 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 196 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 197 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 198 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 199 200 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 201 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 202 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 203 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 204 205 /* ID_AA64MMFR2_EL1 definitions */ 206 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 207 208 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 209 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 210 211 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 212 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 213 214 /* ID_AA64PFR1_EL1 definitions */ 215 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 216 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 217 218 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 219 220 /* ID_PFR1_EL1 definitions */ 221 #define ID_PFR1_VIRTEXT_SHIFT U(12) 222 #define ID_PFR1_VIRTEXT_MASK U(0xf) 223 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 224 & ID_PFR1_VIRTEXT_MASK) 225 226 /* SCTLR definitions */ 227 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 228 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 229 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 230 231 #define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 232 (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) 233 #define SCTLR_AARCH32_EL1_RES1 \ 234 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 235 (U(1) << 4) | (U(1) << 3)) 236 237 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 238 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 239 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 240 241 #define SCTLR_M_BIT (ULL(1) << 0) 242 #define SCTLR_A_BIT (ULL(1) << 1) 243 #define SCTLR_C_BIT (ULL(1) << 2) 244 #define SCTLR_SA_BIT (ULL(1) << 3) 245 #define SCTLR_SA0_BIT (ULL(1) << 4) 246 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 247 #define SCTLR_ITD_BIT (ULL(1) << 7) 248 #define SCTLR_SED_BIT (ULL(1) << 8) 249 #define SCTLR_UMA_BIT (ULL(1) << 9) 250 #define SCTLR_I_BIT (ULL(1) << 12) 251 #define SCTLR_V_BIT (ULL(1) << 13) 252 #define SCTLR_DZE_BIT (ULL(1) << 14) 253 #define SCTLR_UCT_BIT (ULL(1) << 15) 254 #define SCTLR_NTWI_BIT (ULL(1) << 16) 255 #define SCTLR_NTWE_BIT (ULL(1) << 18) 256 #define SCTLR_WXN_BIT (ULL(1) << 19) 257 #define SCTLR_UWXN_BIT (ULL(1) << 20) 258 #define SCTLR_IESB_BIT (ULL(1) << 21) 259 #define SCTLR_E0E_BIT (ULL(1) << 24) 260 #define SCTLR_EE_BIT (ULL(1) << 25) 261 #define SCTLR_UCI_BIT (ULL(1) << 26) 262 #define SCTLR_EnIA_BIT (ULL(1) << 31) 263 #define SCTLR_DSSBS_BIT (ULL(1) << 44) 264 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 265 266 /* CPACR_El1 definitions */ 267 #define CPACR_EL1_FPEN(x) ((x) << 20) 268 #define CPACR_EL1_FP_TRAP_EL0 U(0x1) 269 #define CPACR_EL1_FP_TRAP_ALL U(0x2) 270 #define CPACR_EL1_FP_TRAP_NONE U(0x3) 271 272 /* SCR definitions */ 273 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 274 #define SCR_FIEN_BIT (U(1) << 21) 275 #define SCR_API_BIT (U(1) << 17) 276 #define SCR_APK_BIT (U(1) << 16) 277 #define SCR_TWE_BIT (U(1) << 13) 278 #define SCR_TWI_BIT (U(1) << 12) 279 #define SCR_ST_BIT (U(1) << 11) 280 #define SCR_RW_BIT (U(1) << 10) 281 #define SCR_SIF_BIT (U(1) << 9) 282 #define SCR_HCE_BIT (U(1) << 8) 283 #define SCR_SMD_BIT (U(1) << 7) 284 #define SCR_EA_BIT (U(1) << 3) 285 #define SCR_FIQ_BIT (U(1) << 2) 286 #define SCR_IRQ_BIT (U(1) << 1) 287 #define SCR_NS_BIT (U(1) << 0) 288 #define SCR_VALID_BIT_MASK U(0x2f8f) 289 #define SCR_RESET_VAL SCR_RES1_BITS 290 291 /* MDCR_EL3 definitions */ 292 #define MDCR_SPD32(x) ((x) << 14) 293 #define MDCR_SPD32_LEGACY ULL(0x0) 294 #define MDCR_SPD32_DISABLE ULL(0x2) 295 #define MDCR_SPD32_ENABLE ULL(0x3) 296 #define MDCR_SDD_BIT (ULL(1) << 16) 297 #define MDCR_NSPB(x) ((x) << 12) 298 #define MDCR_NSPB_EL1 ULL(0x3) 299 #define MDCR_TDOSA_BIT (ULL(1) << 10) 300 #define MDCR_TDA_BIT (ULL(1) << 9) 301 #define MDCR_TPM_BIT (ULL(1) << 6) 302 #define MDCR_SCCD_BIT (ULL(1) << 23) 303 #define MDCR_EL3_RESET_VAL ULL(0x0) 304 305 /* MDCR_EL2 definitions */ 306 #define MDCR_EL2_TPMS (U(1) << 14) 307 #define MDCR_EL2_E2PB(x) ((x) << 12) 308 #define MDCR_EL2_E2PB_EL1 U(0x3) 309 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 310 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 311 #define MDCR_EL2_TDA_BIT (U(1) << 9) 312 #define MDCR_EL2_TDE_BIT (U(1) << 8) 313 #define MDCR_EL2_HPME_BIT (U(1) << 7) 314 #define MDCR_EL2_TPM_BIT (U(1) << 6) 315 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 316 #define MDCR_EL2_RESET_VAL U(0x0) 317 318 /* HSTR_EL2 definitions */ 319 #define HSTR_EL2_RESET_VAL U(0x0) 320 #define HSTR_EL2_T_MASK U(0xff) 321 322 /* CNTHP_CTL_EL2 definitions */ 323 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 324 #define CNTHP_CTL_RESET_VAL U(0x0) 325 326 /* VTTBR_EL2 definitions */ 327 #define VTTBR_RESET_VAL ULL(0x0) 328 #define VTTBR_VMID_MASK ULL(0xff) 329 #define VTTBR_VMID_SHIFT U(48) 330 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 331 #define VTTBR_BADDR_SHIFT U(0) 332 333 /* HCR definitions */ 334 #define HCR_API_BIT (ULL(1) << 41) 335 #define HCR_APK_BIT (ULL(1) << 40) 336 #define HCR_TGE_BIT (ULL(1) << 27) 337 #define HCR_RW_SHIFT U(31) 338 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 339 #define HCR_AMO_BIT (ULL(1) << 5) 340 #define HCR_IMO_BIT (ULL(1) << 4) 341 #define HCR_FMO_BIT (ULL(1) << 3) 342 343 /* ISR definitions */ 344 #define ISR_A_SHIFT U(8) 345 #define ISR_I_SHIFT U(7) 346 #define ISR_F_SHIFT U(6) 347 348 /* CNTHCTL_EL2 definitions */ 349 #define CNTHCTL_RESET_VAL U(0x0) 350 #define EVNTEN_BIT (U(1) << 2) 351 #define EL1PCEN_BIT (U(1) << 1) 352 #define EL1PCTEN_BIT (U(1) << 0) 353 354 /* CNTKCTL_EL1 definitions */ 355 #define EL0PTEN_BIT (U(1) << 9) 356 #define EL0VTEN_BIT (U(1) << 8) 357 #define EL0PCTEN_BIT (U(1) << 0) 358 #define EL0VCTEN_BIT (U(1) << 1) 359 #define EVNTEN_BIT (U(1) << 2) 360 #define EVNTDIR_BIT (U(1) << 3) 361 #define EVNTI_SHIFT U(4) 362 #define EVNTI_MASK U(0xf) 363 364 /* CPTR_EL3 definitions */ 365 #define TCPAC_BIT (U(1) << 31) 366 #define TAM_BIT (U(1) << 30) 367 #define TTA_BIT (U(1) << 20) 368 #define TFP_BIT (U(1) << 10) 369 #define CPTR_EZ_BIT (U(1) << 8) 370 #define CPTR_EL3_RESET_VAL U(0x0) 371 372 /* CPTR_EL2 definitions */ 373 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 374 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 375 #define CPTR_EL2_TAM_BIT (U(1) << 30) 376 #define CPTR_EL2_TTA_BIT (U(1) << 20) 377 #define CPTR_EL2_TFP_BIT (U(1) << 10) 378 #define CPTR_EL2_TZ_BIT (U(1) << 8) 379 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 380 381 /* CPSR/SPSR definitions */ 382 #define DAIF_FIQ_BIT (U(1) << 0) 383 #define DAIF_IRQ_BIT (U(1) << 1) 384 #define DAIF_ABT_BIT (U(1) << 2) 385 #define DAIF_DBG_BIT (U(1) << 3) 386 #define SPSR_DAIF_SHIFT U(6) 387 #define SPSR_DAIF_MASK U(0xf) 388 389 #define SPSR_AIF_SHIFT U(6) 390 #define SPSR_AIF_MASK U(0x7) 391 392 #define SPSR_E_SHIFT U(9) 393 #define SPSR_E_MASK U(0x1) 394 #define SPSR_E_LITTLE U(0x0) 395 #define SPSR_E_BIG U(0x1) 396 397 #define SPSR_T_SHIFT U(5) 398 #define SPSR_T_MASK U(0x1) 399 #define SPSR_T_ARM U(0x0) 400 #define SPSR_T_THUMB U(0x1) 401 402 #define SPSR_M_SHIFT U(4) 403 #define SPSR_M_MASK U(0x1) 404 #define SPSR_M_AARCH64 U(0x0) 405 #define SPSR_M_AARCH32 U(0x1) 406 407 #define DISABLE_ALL_EXCEPTIONS \ 408 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 409 410 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 411 412 /* 413 * RMR_EL3 definitions 414 */ 415 #define RMR_EL3_RR_BIT (U(1) << 1) 416 #define RMR_EL3_AA64_BIT (U(1) << 0) 417 418 /* 419 * HI-VECTOR address for AArch32 state 420 */ 421 #define HI_VECTOR_BASE U(0xFFFF0000) 422 423 /* 424 * TCR defintions 425 */ 426 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 427 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 428 #define TCR_EL1_IPS_SHIFT U(32) 429 #define TCR_EL2_PS_SHIFT U(16) 430 #define TCR_EL3_PS_SHIFT U(16) 431 432 #define TCR_TxSZ_MIN ULL(16) 433 #define TCR_TxSZ_MAX ULL(39) 434 #define TCR_TxSZ_MAX_TTST ULL(48) 435 436 /* (internal) physical address size bits in EL3/EL1 */ 437 #define TCR_PS_BITS_4GB ULL(0x0) 438 #define TCR_PS_BITS_64GB ULL(0x1) 439 #define TCR_PS_BITS_1TB ULL(0x2) 440 #define TCR_PS_BITS_4TB ULL(0x3) 441 #define TCR_PS_BITS_16TB ULL(0x4) 442 #define TCR_PS_BITS_256TB ULL(0x5) 443 444 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 445 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 446 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 447 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 448 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 449 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 450 451 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 452 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 453 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 454 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 455 456 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 457 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 458 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 459 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 460 461 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 462 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 463 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 464 465 #define TCR_TG0_SHIFT U(14) 466 #define TCR_TG0_MASK ULL(3) 467 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 468 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 469 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 470 471 #define TCR_EPD0_BIT (ULL(1) << 7) 472 #define TCR_EPD1_BIT (ULL(1) << 23) 473 474 #define MODE_SP_SHIFT U(0x0) 475 #define MODE_SP_MASK U(0x1) 476 #define MODE_SP_EL0 U(0x0) 477 #define MODE_SP_ELX U(0x1) 478 479 #define MODE_RW_SHIFT U(0x4) 480 #define MODE_RW_MASK U(0x1) 481 #define MODE_RW_64 U(0x0) 482 #define MODE_RW_32 U(0x1) 483 484 #define MODE_EL_SHIFT U(0x2) 485 #define MODE_EL_MASK U(0x3) 486 #define MODE_EL3 U(0x3) 487 #define MODE_EL2 U(0x2) 488 #define MODE_EL1 U(0x1) 489 #define MODE_EL0 U(0x0) 490 491 #define MODE32_SHIFT U(0) 492 #define MODE32_MASK U(0xf) 493 #define MODE32_usr U(0x0) 494 #define MODE32_fiq U(0x1) 495 #define MODE32_irq U(0x2) 496 #define MODE32_svc U(0x3) 497 #define MODE32_mon U(0x6) 498 #define MODE32_abt U(0x7) 499 #define MODE32_hyp U(0xa) 500 #define MODE32_und U(0xb) 501 #define MODE32_sys U(0xf) 502 503 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 504 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 505 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 506 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 507 508 #define SPSR_64(el, sp, daif) \ 509 ((MODE_RW_64 << MODE_RW_SHIFT) | \ 510 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 511 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 512 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) 513 514 #define SPSR_MODE32(mode, isa, endian, aif) \ 515 ((MODE_RW_32 << MODE_RW_SHIFT) | \ 516 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 517 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 518 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 519 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) 520 521 /* 522 * TTBR Definitions 523 */ 524 #define TTBR_CNP_BIT ULL(0x1) 525 526 /* 527 * CTR_EL0 definitions 528 */ 529 #define CTR_CWG_SHIFT U(24) 530 #define CTR_CWG_MASK U(0xf) 531 #define CTR_ERG_SHIFT U(20) 532 #define CTR_ERG_MASK U(0xf) 533 #define CTR_DMINLINE_SHIFT U(16) 534 #define CTR_DMINLINE_MASK U(0xf) 535 #define CTR_L1IP_SHIFT U(14) 536 #define CTR_L1IP_MASK U(0x3) 537 #define CTR_IMINLINE_SHIFT U(0) 538 #define CTR_IMINLINE_MASK U(0xf) 539 540 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 541 542 /* Physical timer control register bit fields shifts and masks */ 543 #define CNTP_CTL_ENABLE_SHIFT U(0) 544 #define CNTP_CTL_IMASK_SHIFT U(1) 545 #define CNTP_CTL_ISTATUS_SHIFT U(2) 546 547 #define CNTP_CTL_ENABLE_MASK U(1) 548 #define CNTP_CTL_IMASK_MASK U(1) 549 #define CNTP_CTL_ISTATUS_MASK U(1) 550 551 /* Exception Syndrome register bits and bobs */ 552 #define ESR_EC_SHIFT U(26) 553 #define ESR_EC_MASK U(0x3f) 554 #define ESR_EC_LENGTH U(6) 555 #define EC_UNKNOWN U(0x0) 556 #define EC_WFE_WFI U(0x1) 557 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 558 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 559 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 560 #define EC_AARCH32_CP14_LDC_STC U(0x6) 561 #define EC_FP_SIMD U(0x7) 562 #define EC_AARCH32_CP10_MRC U(0x8) 563 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 564 #define EC_ILLEGAL U(0xe) 565 #define EC_AARCH32_SVC U(0x11) 566 #define EC_AARCH32_HVC U(0x12) 567 #define EC_AARCH32_SMC U(0x13) 568 #define EC_AARCH64_SVC U(0x15) 569 #define EC_AARCH64_HVC U(0x16) 570 #define EC_AARCH64_SMC U(0x17) 571 #define EC_AARCH64_SYS U(0x18) 572 #define EC_IABORT_LOWER_EL U(0x20) 573 #define EC_IABORT_CUR_EL U(0x21) 574 #define EC_PC_ALIGN U(0x22) 575 #define EC_DABORT_LOWER_EL U(0x24) 576 #define EC_DABORT_CUR_EL U(0x25) 577 #define EC_SP_ALIGN U(0x26) 578 #define EC_AARCH32_FP U(0x28) 579 #define EC_AARCH64_FP U(0x2c) 580 #define EC_SERROR U(0x2f) 581 582 /* 583 * External Abort bit in Instruction and Data Aborts synchronous exception 584 * syndromes. 585 */ 586 #define ESR_ISS_EABORT_EA_BIT U(9) 587 588 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 589 590 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 591 #define RMR_RESET_REQUEST_SHIFT U(0x1) 592 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 593 594 /******************************************************************************* 595 * Definitions of register offsets, fields and macros for CPU system 596 * instructions. 597 ******************************************************************************/ 598 599 #define TLBI_ADDR_SHIFT U(12) 600 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 601 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 602 603 /******************************************************************************* 604 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 605 * system level implementation of the Generic Timer. 606 ******************************************************************************/ 607 #define CNTCTLBASE_CNTFRQ U(0x0) 608 #define CNTNSAR U(0x4) 609 #define CNTNSAR_NS_SHIFT(x) (x) 610 611 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 612 #define CNTACR_RPCT_SHIFT U(0x0) 613 #define CNTACR_RVCT_SHIFT U(0x1) 614 #define CNTACR_RFRQ_SHIFT U(0x2) 615 #define CNTACR_RVOFF_SHIFT U(0x3) 616 #define CNTACR_RWVT_SHIFT U(0x4) 617 #define CNTACR_RWPT_SHIFT U(0x5) 618 619 /******************************************************************************* 620 * Definitions of register offsets and fields in the CNTBaseN Frame of the 621 * system level implementation of the Generic Timer. 622 ******************************************************************************/ 623 /* Physical Count register. */ 624 #define CNTPCT_LO U(0x0) 625 /* Counter Frequency register. */ 626 #define CNTBASEN_CNTFRQ U(0x10) 627 /* Physical Timer CompareValue register. */ 628 #define CNTP_CVAL_LO U(0x20) 629 /* Physical Timer Control register. */ 630 #define CNTP_CTL U(0x2c) 631 632 /* PMCR_EL0 definitions */ 633 #define PMCR_EL0_RESET_VAL U(0x0) 634 #define PMCR_EL0_N_SHIFT U(11) 635 #define PMCR_EL0_N_MASK U(0x1f) 636 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 637 #define PMCR_EL0_LC_BIT (U(1) << 6) 638 #define PMCR_EL0_DP_BIT (U(1) << 5) 639 #define PMCR_EL0_X_BIT (U(1) << 4) 640 #define PMCR_EL0_D_BIT (U(1) << 3) 641 642 /******************************************************************************* 643 * Definitions for system register interface to SVE 644 ******************************************************************************/ 645 #define ZCR_EL3 S3_6_C1_C2_0 646 #define ZCR_EL2 S3_4_C1_C2_0 647 648 /* ZCR_EL3 definitions */ 649 #define ZCR_EL3_LEN_MASK U(0xf) 650 651 /* ZCR_EL2 definitions */ 652 #define ZCR_EL2_LEN_MASK U(0xf) 653 654 /******************************************************************************* 655 * Definitions of MAIR encodings for device and normal memory 656 ******************************************************************************/ 657 /* 658 * MAIR encodings for device memory attributes. 659 */ 660 #define MAIR_DEV_nGnRnE ULL(0x0) 661 #define MAIR_DEV_nGnRE ULL(0x4) 662 #define MAIR_DEV_nGRE ULL(0x8) 663 #define MAIR_DEV_GRE ULL(0xc) 664 665 /* 666 * MAIR encodings for normal memory attributes. 667 * 668 * Cache Policy 669 * WT: Write Through 670 * WB: Write Back 671 * NC: Non-Cacheable 672 * 673 * Transient Hint 674 * NTR: Non-Transient 675 * TR: Transient 676 * 677 * Allocation Policy 678 * RA: Read Allocate 679 * WA: Write Allocate 680 * RWA: Read and Write Allocate 681 * NA: No Allocation 682 */ 683 #define MAIR_NORM_WT_TR_WA ULL(0x1) 684 #define MAIR_NORM_WT_TR_RA ULL(0x2) 685 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 686 #define MAIR_NORM_NC ULL(0x4) 687 #define MAIR_NORM_WB_TR_WA ULL(0x5) 688 #define MAIR_NORM_WB_TR_RA ULL(0x6) 689 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 690 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 691 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 692 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 693 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 694 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 695 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 696 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 697 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 698 699 #define MAIR_NORM_OUTER_SHIFT U(4) 700 701 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 702 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 703 704 /* PAR_EL1 fields */ 705 #define PAR_F_SHIFT U(0) 706 #define PAR_F_MASK ULL(0x1) 707 #define PAR_ADDR_SHIFT U(12) 708 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 709 710 /******************************************************************************* 711 * Definitions for system register interface to SPE 712 ******************************************************************************/ 713 #define PMBLIMITR_EL1 S3_0_C9_C10_0 714 715 /******************************************************************************* 716 * Definitions for system register interface to MPAM 717 ******************************************************************************/ 718 #define MPAMIDR_EL1 S3_0_C10_C4_4 719 #define MPAM2_EL2 S3_4_C10_C5_0 720 #define MPAMHCR_EL2 S3_4_C10_C4_0 721 #define MPAM3_EL3 S3_6_C10_C5_0 722 723 /******************************************************************************* 724 * Definitions for system register interface to AMU for ARMv8.4 onwards 725 ******************************************************************************/ 726 #define AMCR_EL0 S3_3_C13_C2_0 727 #define AMCFGR_EL0 S3_3_C13_C2_1 728 #define AMCGCR_EL0 S3_3_C13_C2_2 729 #define AMUSERENR_EL0 S3_3_C13_C2_3 730 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 731 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 732 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 733 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 734 735 /* Activity Monitor Group 0 Event Counter Registers */ 736 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 737 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 738 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 739 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 740 741 /* Activity Monitor Group 0 Event Type Registers */ 742 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 743 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 744 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 745 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 746 747 /* Activity Monitor Group 1 Event Counter Registers */ 748 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 749 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 750 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 751 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 752 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 753 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 754 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 755 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 756 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 757 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 758 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 759 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 760 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 761 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 762 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 763 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 764 765 /* Activity Monitor Group 1 Event Type Registers */ 766 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 767 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 768 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 769 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 770 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 771 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 772 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 773 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 774 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 775 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 776 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 777 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 778 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 779 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 780 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 781 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 782 783 /* AMCGCR_EL0 definitions */ 784 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 785 #define AMCGCR_EL0_CG1NC_LENGTH U(8) 786 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 787 788 /* MPAM register definitions */ 789 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 790 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 791 792 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 793 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 794 795 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 796 797 /******************************************************************************* 798 * RAS system registers 799 ******************************************************************************/ 800 #define DISR_EL1 S3_0_C12_C1_1 801 #define DISR_A_BIT U(31) 802 803 #define ERRIDR_EL1 S3_0_C5_C3_0 804 #define ERRIDR_MASK U(0xffff) 805 806 #define ERRSELR_EL1 S3_0_C5_C3_1 807 808 /* System register access to Standard Error Record registers */ 809 #define ERXFR_EL1 S3_0_C5_C4_0 810 #define ERXCTLR_EL1 S3_0_C5_C4_1 811 #define ERXSTATUS_EL1 S3_0_C5_C4_2 812 #define ERXADDR_EL1 S3_0_C5_C4_3 813 #define ERXPFGF_EL1 S3_0_C5_C4_4 814 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 815 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 816 #define ERXMISC0_EL1 S3_0_C5_C5_0 817 #define ERXMISC1_EL1 S3_0_C5_C5_1 818 819 #define ERXCTLR_ED_BIT (U(1) << 0) 820 #define ERXCTLR_UE_BIT (U(1) << 4) 821 822 #define ERXPFGCTL_UC_BIT (U(1) << 1) 823 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 824 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 825 826 /******************************************************************************* 827 * Armv8.3 Pointer Authentication Registers 828 ******************************************************************************/ 829 #define APIAKeyLo_EL1 S3_0_C2_C1_0 830 #define APIAKeyHi_EL1 S3_0_C2_C1_1 831 #define APIBKeyLo_EL1 S3_0_C2_C1_2 832 #define APIBKeyHi_EL1 S3_0_C2_C1_3 833 #define APDAKeyLo_EL1 S3_0_C2_C2_0 834 #define APDAKeyHi_EL1 S3_0_C2_C2_1 835 #define APDBKeyLo_EL1 S3_0_C2_C2_2 836 #define APDBKeyHi_EL1 S3_0_C2_C2_3 837 #define APGAKeyLo_EL1 S3_0_C2_C3_0 838 #define APGAKeyHi_EL1 S3_0_C2_C3_1 839 840 /******************************************************************************* 841 * Armv8.4 Data Independent Timing Registers 842 ******************************************************************************/ 843 #define DIT S3_3_C4_C2_5 844 #define DIT_BIT BIT(24) 845 846 /******************************************************************************* 847 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 848 ******************************************************************************/ 849 #define SSBS S3_3_C4_C2_6 850 851 #endif /* ARCH_H */ 852