1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLY__ 18 #include <drivers/st/stm32mp1_clk.h> 19 20 #include <boot_api.h> 21 #include <stm32mp_common.h> 22 #include <stm32mp_dt.h> 23 #include <stm32mp_shres_helpers.h> 24 #include <stm32mp1_private.h> 25 #endif 26 27 /******************************************************************************* 28 * STM32MP1 memory map related constants 29 ******************************************************************************/ 30 31 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 32 #define STM32MP_SYSRAM_SIZE U(0x00040000) 33 34 /* DDR configuration */ 35 #define STM32MP_DDR_BASE U(0xC0000000) 36 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 37 #define STM32MP_DDR_SPEED_DFLT 528 38 39 /* DDR power initializations */ 40 #ifndef __ASSEMBLY__ 41 enum ddr_type { 42 STM32MP_DDR3, 43 STM32MP_LPDDR2, 44 }; 45 #endif 46 47 /* Section used inside TF binaries */ 48 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */ 49 /* 256 Octets reserved for header */ 50 #define STM32MP_HEADER_SIZE U(0x00000100) 51 52 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 53 STM32MP_PARAM_LOAD_SIZE + \ 54 STM32MP_HEADER_SIZE) 55 56 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 57 (STM32MP_PARAM_LOAD_SIZE + \ 58 STM32MP_HEADER_SIZE)) 59 60 #if STACK_PROTECTOR_ENABLED 61 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */ 62 #else 63 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */ 64 #endif 65 66 #define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \ 67 STM32MP_SYSRAM_SIZE - \ 68 STM32MP_BL32_SIZE) 69 70 #if STACK_PROTECTOR_ENABLED 71 #define STM32MP_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */ 72 #else 73 #define STM32MP_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */ 74 #endif 75 76 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 77 STM32MP_BL2_SIZE) 78 79 /* BL2 and BL32/sp_min require 5 tables */ 80 #define MAX_XLAT_TABLES 5 81 82 /* 83 * MAX_MMAP_REGIONS is usually: 84 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 85 */ 86 #if defined(IMAGE_BL2) 87 #define MAX_MMAP_REGIONS 11 88 #endif 89 #if defined(IMAGE_BL32) 90 #define MAX_MMAP_REGIONS 6 91 #endif 92 93 /* DTB initialization value */ 94 #define STM32MP_DTB_SIZE U(0x00004000) /* 16Ko for DTB */ 95 96 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 97 STM32MP_DTB_SIZE) 98 99 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 100 101 /******************************************************************************* 102 * STM32MP1 device/io map related constants (used for MMU) 103 ******************************************************************************/ 104 #define STM32MP1_DEVICE1_BASE U(0x40000000) 105 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 106 107 #define STM32MP1_DEVICE2_BASE U(0x80000000) 108 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 109 110 /******************************************************************************* 111 * STM32MP1 RCC 112 ******************************************************************************/ 113 #define RCC_BASE U(0x50000000) 114 115 /******************************************************************************* 116 * STM32MP1 PWR 117 ******************************************************************************/ 118 #define PWR_BASE U(0x50001000) 119 120 /******************************************************************************* 121 * STM32MP1 GPIO 122 ******************************************************************************/ 123 #define GPIOA_BASE U(0x50002000) 124 #define GPIOB_BASE U(0x50003000) 125 #define GPIOC_BASE U(0x50004000) 126 #define GPIOD_BASE U(0x50005000) 127 #define GPIOE_BASE U(0x50006000) 128 #define GPIOF_BASE U(0x50007000) 129 #define GPIOG_BASE U(0x50008000) 130 #define GPIOH_BASE U(0x50009000) 131 #define GPIOI_BASE U(0x5000A000) 132 #define GPIOJ_BASE U(0x5000B000) 133 #define GPIOK_BASE U(0x5000C000) 134 #define GPIOZ_BASE U(0x54004000) 135 #define GPIO_BANK_OFFSET U(0x1000) 136 137 /* Bank IDs used in GPIO driver API */ 138 #define GPIO_BANK_A U(0) 139 #define GPIO_BANK_B U(1) 140 #define GPIO_BANK_C U(2) 141 #define GPIO_BANK_D U(3) 142 #define GPIO_BANK_E U(4) 143 #define GPIO_BANK_F U(5) 144 #define GPIO_BANK_G U(6) 145 #define GPIO_BANK_H U(7) 146 #define GPIO_BANK_I U(8) 147 #define GPIO_BANK_J U(9) 148 #define GPIO_BANK_K U(10) 149 #define GPIO_BANK_Z U(25) 150 151 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 152 153 /******************************************************************************* 154 * STM32MP1 UART 155 ******************************************************************************/ 156 #define USART1_BASE U(0x5C000000) 157 #define USART2_BASE U(0x4000E000) 158 #define USART3_BASE U(0x4000F000) 159 #define UART4_BASE U(0x40010000) 160 #define UART5_BASE U(0x40011000) 161 #define USART6_BASE U(0x44003000) 162 #define UART7_BASE U(0x40018000) 163 #define UART8_BASE U(0x40019000) 164 #define STM32MP_UART_BAUDRATE U(115200) 165 166 /* For UART crash console */ 167 #define STM32MP_DEBUG_USART_BASE UART4_BASE 168 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 169 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 170 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 171 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 172 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 173 #define DEBUG_UART_TX_GPIO_PORT 11 174 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 175 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 176 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 177 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 178 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 179 180 /******************************************************************************* 181 * STM32MP1 TZC (TZ400) 182 ******************************************************************************/ 183 #define STM32MP1_TZC_BASE U(0x5C006000) 184 185 #define STM32MP1_TZC_A7_ID U(0) 186 #define STM32MP1_TZC_M4_ID U(1) 187 #define STM32MP1_TZC_LCD_ID U(3) 188 #define STM32MP1_TZC_GPU_ID U(4) 189 #define STM32MP1_TZC_MDMA_ID U(5) 190 #define STM32MP1_TZC_DMA_ID U(6) 191 #define STM32MP1_TZC_USB_HOST_ID U(7) 192 #define STM32MP1_TZC_USB_OTG_ID U(8) 193 #define STM32MP1_TZC_SDMMC_ID U(9) 194 #define STM32MP1_TZC_ETH_ID U(10) 195 #define STM32MP1_TZC_DAP_ID U(15) 196 197 #define STM32MP1_FILTER_BIT_ALL U(3) 198 199 /******************************************************************************* 200 * STM32MP1 SDMMC 201 ******************************************************************************/ 202 #define STM32MP_SDMMC1_BASE U(0x58005000) 203 #define STM32MP_SDMMC2_BASE U(0x58007000) 204 #define STM32MP_SDMMC3_BASE U(0x48004000) 205 206 #define STM32MP_MMC_INIT_FREQ 400000 /*400 KHz*/ 207 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ 25000000 /*25 MHz*/ 208 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ 50000000 /*50 MHz*/ 209 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/ 210 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/ 211 212 /******************************************************************************* 213 * STM32MP1 BSEC / OTP 214 ******************************************************************************/ 215 #define STM32MP1_OTP_MAX_ID 0x5FU 216 #define STM32MP1_UPPER_OTP_START 0x20U 217 218 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 219 220 /* OTP offsets */ 221 #define DATA0_OTP U(0) 222 223 /* OTP mask */ 224 /* DATA0 */ 225 #define DATA0_OTP_SECURED BIT(6) 226 227 /******************************************************************************* 228 * STM32MP1 TAMP 229 ******************************************************************************/ 230 #define TAMP_BASE U(0x5C00A000) 231 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 232 233 #if !(defined(__LINKER__) || defined(__ASSEMBLY__)) 234 static inline uint32_t tamp_bkpr(uint32_t idx) 235 { 236 return TAMP_BKP_REGISTER_BASE + (idx << 2); 237 } 238 #endif 239 240 /******************************************************************************* 241 * STM32MP1 DDRCTRL 242 ******************************************************************************/ 243 #define DDRCTRL_BASE U(0x5A003000) 244 245 /******************************************************************************* 246 * STM32MP1 DDRPHYC 247 ******************************************************************************/ 248 #define DDRPHYC_BASE U(0x5A004000) 249 250 /******************************************************************************* 251 * STM32MP1 I2C4 252 ******************************************************************************/ 253 #define I2C4_BASE U(0x5C002000) 254 255 /******************************************************************************* 256 * Device Tree defines 257 ******************************************************************************/ 258 #define DT_PWR_COMPAT "st,stm32mp1-pwr" 259 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 260 261 #endif /* STM32MP1_DEF_H */ 262