1/* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl32/tsp/tsp.h> 10#include <lib/xlat_tables/xlat_tables_defs.h> 11 12#include "../tsp_private.h" 13 14 15 .globl tsp_entrypoint 16 .globl tsp_vector_table 17 18 19 20 /* --------------------------------------------- 21 * Populate the params in x0-x7 from the pointer 22 * to the smc args structure in x0. 23 * --------------------------------------------- 24 */ 25 .macro restore_args_call_smc 26 ldp x6, x7, [x0, #TSP_ARG6] 27 ldp x4, x5, [x0, #TSP_ARG4] 28 ldp x2, x3, [x0, #TSP_ARG2] 29 ldp x0, x1, [x0, #TSP_ARG0] 30 smc #0 31 .endm 32 33 .macro save_eret_context reg1 reg2 34 mrs \reg1, elr_el1 35 mrs \reg2, spsr_el1 36 stp \reg1, \reg2, [sp, #-0x10]! 37 stp x30, x18, [sp, #-0x10]! 38 .endm 39 40 .macro restore_eret_context reg1 reg2 41 ldp x30, x18, [sp], #0x10 42 ldp \reg1, \reg2, [sp], #0x10 43 msr elr_el1, \reg1 44 msr spsr_el1, \reg2 45 .endm 46 47func tsp_entrypoint _align=3 48 49 /* --------------------------------------------- 50 * Set the exception vector to something sane. 51 * --------------------------------------------- 52 */ 53 adr x0, tsp_exceptions 54 msr vbar_el1, x0 55 isb 56 57 /* --------------------------------------------- 58 * Enable the SError interrupt now that the 59 * exception vectors have been setup. 60 * --------------------------------------------- 61 */ 62 msr daifclr, #DAIF_ABT_BIT 63 64 /* --------------------------------------------- 65 * Enable the instruction cache, stack pointer 66 * and data access alignment checks 67 * --------------------------------------------- 68 */ 69 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 70 mrs x0, sctlr_el1 71 orr x0, x0, x1 72 msr sctlr_el1, x0 73 isb 74 75 /* --------------------------------------------- 76 * Invalidate the RW memory used by the BL32 77 * image. This includes the data and NOBITS 78 * sections. This is done to safeguard against 79 * possible corruption of this memory by dirty 80 * cache lines in a system cache as a result of 81 * use by an earlier boot loader stage. 82 * --------------------------------------------- 83 */ 84 adr x0, __RW_START__ 85 adr x1, __RW_END__ 86 sub x1, x1, x0 87 bl inv_dcache_range 88 89 /* --------------------------------------------- 90 * Zero out NOBITS sections. There are 2 of them: 91 * - the .bss section; 92 * - the coherent memory section. 93 * --------------------------------------------- 94 */ 95 ldr x0, =__BSS_START__ 96 ldr x1, =__BSS_SIZE__ 97 bl zeromem 98 99#if USE_COHERENT_MEM 100 ldr x0, =__COHERENT_RAM_START__ 101 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 102 bl zeromem 103#endif 104 105 /* -------------------------------------------- 106 * Allocate a stack whose memory will be marked 107 * as Normal-IS-WBWA when the MMU is enabled. 108 * There is no risk of reading stale stack 109 * memory after enabling the MMU as only the 110 * primary cpu is running at the moment. 111 * -------------------------------------------- 112 */ 113 bl plat_set_my_stack 114 115 /* --------------------------------------------- 116 * Initialize the stack protector canary before 117 * any C code is called. 118 * --------------------------------------------- 119 */ 120#if STACK_PROTECTOR_ENABLED 121 bl update_stack_protector_canary 122#endif 123 124 /* --------------------------------------------- 125 * Perform TSP setup 126 * --------------------------------------------- 127 */ 128 bl tsp_setup 129 130 /* --------------------------------------------- 131 * Enable pointer authentication 132 * --------------------------------------------- 133 */ 134#if ENABLE_PAUTH 135 mrs x0, sctlr_el1 136 orr x0, x0, #SCTLR_EnIA_BIT 137 msr sctlr_el1, x0 138 isb 139#endif /* ENABLE_PAUTH */ 140 141 /* --------------------------------------------- 142 * Jump to main function. 143 * --------------------------------------------- 144 */ 145 bl tsp_main 146 147 /* --------------------------------------------- 148 * Tell TSPD that we are done initialising 149 * --------------------------------------------- 150 */ 151 mov x1, x0 152 mov x0, #TSP_ENTRY_DONE 153 smc #0 154 155tsp_entrypoint_panic: 156 b tsp_entrypoint_panic 157endfunc tsp_entrypoint 158 159 160 /* ------------------------------------------- 161 * Table of entrypoint vectors provided to the 162 * TSPD for the various entrypoints 163 * ------------------------------------------- 164 */ 165func tsp_vector_table 166 b tsp_yield_smc_entry 167 b tsp_fast_smc_entry 168 b tsp_cpu_on_entry 169 b tsp_cpu_off_entry 170 b tsp_cpu_resume_entry 171 b tsp_cpu_suspend_entry 172 b tsp_sel1_intr_entry 173 b tsp_system_off_entry 174 b tsp_system_reset_entry 175 b tsp_abort_yield_smc_entry 176endfunc tsp_vector_table 177 178 /*--------------------------------------------- 179 * This entrypoint is used by the TSPD when this 180 * cpu is to be turned off through a CPU_OFF 181 * psci call to ask the TSP to perform any 182 * bookeeping necessary. In the current 183 * implementation, the TSPD expects the TSP to 184 * re-initialise its state so nothing is done 185 * here except for acknowledging the request. 186 * --------------------------------------------- 187 */ 188func tsp_cpu_off_entry 189 bl tsp_cpu_off_main 190 restore_args_call_smc 191endfunc tsp_cpu_off_entry 192 193 /*--------------------------------------------- 194 * This entrypoint is used by the TSPD when the 195 * system is about to be switched off (through 196 * a SYSTEM_OFF psci call) to ask the TSP to 197 * perform any necessary bookkeeping. 198 * --------------------------------------------- 199 */ 200func tsp_system_off_entry 201 bl tsp_system_off_main 202 restore_args_call_smc 203endfunc tsp_system_off_entry 204 205 /*--------------------------------------------- 206 * This entrypoint is used by the TSPD when the 207 * system is about to be reset (through a 208 * SYSTEM_RESET psci call) to ask the TSP to 209 * perform any necessary bookkeeping. 210 * --------------------------------------------- 211 */ 212func tsp_system_reset_entry 213 bl tsp_system_reset_main 214 restore_args_call_smc 215endfunc tsp_system_reset_entry 216 217 /*--------------------------------------------- 218 * This entrypoint is used by the TSPD when this 219 * cpu is turned on using a CPU_ON psci call to 220 * ask the TSP to initialise itself i.e. setup 221 * the mmu, stacks etc. Minimal architectural 222 * state will be initialised by the TSPD when 223 * this function is entered i.e. Caches and MMU 224 * will be turned off, the execution state 225 * will be aarch64 and exceptions masked. 226 * --------------------------------------------- 227 */ 228func tsp_cpu_on_entry 229 /* --------------------------------------------- 230 * Set the exception vector to something sane. 231 * --------------------------------------------- 232 */ 233 adr x0, tsp_exceptions 234 msr vbar_el1, x0 235 isb 236 237 /* Enable the SError interrupt */ 238 msr daifclr, #DAIF_ABT_BIT 239 240 /* --------------------------------------------- 241 * Enable the instruction cache, stack pointer 242 * and data access alignment checks 243 * --------------------------------------------- 244 */ 245 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 246 mrs x0, sctlr_el1 247 orr x0, x0, x1 248 msr sctlr_el1, x0 249 isb 250 251 /* -------------------------------------------- 252 * Give ourselves a stack whose memory will be 253 * marked as Normal-IS-WBWA when the MMU is 254 * enabled. 255 * -------------------------------------------- 256 */ 257 bl plat_set_my_stack 258 259 /* -------------------------------------------- 260 * Enable MMU and D-caches together. 261 * -------------------------------------------- 262 */ 263 mov x0, #0 264 bl bl32_plat_enable_mmu 265 266 /* --------------------------------------------- 267 * Enter C runtime to perform any remaining 268 * book keeping 269 * --------------------------------------------- 270 */ 271 bl tsp_cpu_on_main 272 restore_args_call_smc 273 274 /* Should never reach here */ 275tsp_cpu_on_entry_panic: 276 b tsp_cpu_on_entry_panic 277endfunc tsp_cpu_on_entry 278 279 /*--------------------------------------------- 280 * This entrypoint is used by the TSPD when this 281 * cpu is to be suspended through a CPU_SUSPEND 282 * psci call to ask the TSP to perform any 283 * bookeeping necessary. In the current 284 * implementation, the TSPD saves and restores 285 * the EL1 state. 286 * --------------------------------------------- 287 */ 288func tsp_cpu_suspend_entry 289 bl tsp_cpu_suspend_main 290 restore_args_call_smc 291endfunc tsp_cpu_suspend_entry 292 293 /*------------------------------------------------- 294 * This entrypoint is used by the TSPD to pass 295 * control for `synchronously` handling a S-EL1 296 * Interrupt which was triggered while executing 297 * in normal world. 'x0' contains a magic number 298 * which indicates this. TSPD expects control to 299 * be handed back at the end of interrupt 300 * processing. This is done through an SMC. 301 * The handover agreement is: 302 * 303 * 1. PSTATE.DAIF are set upon entry. 'x1' has 304 * the ELR_EL3 from the non-secure state. 305 * 2. TSP has to preserve the callee saved 306 * general purpose registers, SP_EL1/EL0 and 307 * LR. 308 * 3. TSP has to preserve the system and vfp 309 * registers (if applicable). 310 * 4. TSP can use 'x0-x18' to enable its C 311 * runtime. 312 * 5. TSP returns to TSPD using an SMC with 313 * 'x0' = TSP_HANDLED_S_EL1_INTR 314 * ------------------------------------------------ 315 */ 316func tsp_sel1_intr_entry 317#if DEBUG 318 mov_imm x2, TSP_HANDLE_SEL1_INTR_AND_RETURN 319 cmp x0, x2 320 b.ne tsp_sel1_int_entry_panic 321#endif 322 /*------------------------------------------------- 323 * Save any previous context needed to perform 324 * an exception return from S-EL1 e.g. context 325 * from a previous Non secure Interrupt. 326 * Update statistics and handle the S-EL1 327 * interrupt before returning to the TSPD. 328 * IRQ/FIQs are not enabled since that will 329 * complicate the implementation. Execution 330 * will be transferred back to the normal world 331 * in any case. The handler can return 0 332 * if the interrupt was handled or TSP_PREEMPTED 333 * if the expected interrupt was preempted 334 * by an interrupt that should be handled in EL3 335 * e.g. Group 0 interrupt in GICv3. In both 336 * the cases switch to EL3 using SMC with id 337 * TSP_HANDLED_S_EL1_INTR. Any other return value 338 * from the handler will result in panic. 339 * ------------------------------------------------ 340 */ 341 save_eret_context x2 x3 342 bl tsp_update_sync_sel1_intr_stats 343 bl tsp_common_int_handler 344 /* Check if the S-EL1 interrupt has been handled */ 345 cbnz x0, tsp_sel1_intr_check_preemption 346 b tsp_sel1_intr_return 347tsp_sel1_intr_check_preemption: 348 /* Check if the S-EL1 interrupt has been preempted */ 349 mov_imm x1, TSP_PREEMPTED 350 cmp x0, x1 351 b.ne tsp_sel1_int_entry_panic 352tsp_sel1_intr_return: 353 mov_imm x0, TSP_HANDLED_S_EL1_INTR 354 restore_eret_context x2 x3 355 smc #0 356 357 /* Should never reach here */ 358tsp_sel1_int_entry_panic: 359 no_ret plat_panic_handler 360endfunc tsp_sel1_intr_entry 361 362 /*--------------------------------------------- 363 * This entrypoint is used by the TSPD when this 364 * cpu resumes execution after an earlier 365 * CPU_SUSPEND psci call to ask the TSP to 366 * restore its saved context. In the current 367 * implementation, the TSPD saves and restores 368 * EL1 state so nothing is done here apart from 369 * acknowledging the request. 370 * --------------------------------------------- 371 */ 372func tsp_cpu_resume_entry 373 bl tsp_cpu_resume_main 374 restore_args_call_smc 375 376 /* Should never reach here */ 377 no_ret plat_panic_handler 378endfunc tsp_cpu_resume_entry 379 380 /*--------------------------------------------- 381 * This entrypoint is used by the TSPD to ask 382 * the TSP to service a fast smc request. 383 * --------------------------------------------- 384 */ 385func tsp_fast_smc_entry 386 bl tsp_smc_handler 387 restore_args_call_smc 388 389 /* Should never reach here */ 390 no_ret plat_panic_handler 391endfunc tsp_fast_smc_entry 392 393 /*--------------------------------------------- 394 * This entrypoint is used by the TSPD to ask 395 * the TSP to service a Yielding SMC request. 396 * We will enable preemption during execution 397 * of tsp_smc_handler. 398 * --------------------------------------------- 399 */ 400func tsp_yield_smc_entry 401 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 402 bl tsp_smc_handler 403 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 404 restore_args_call_smc 405 406 /* Should never reach here */ 407 no_ret plat_panic_handler 408endfunc tsp_yield_smc_entry 409 410 /*--------------------------------------------------------------------- 411 * This entrypoint is used by the TSPD to abort a pre-empted Yielding 412 * SMC. It could be on behalf of non-secure world or because a CPU 413 * suspend/CPU off request needs to abort the preempted SMC. 414 * -------------------------------------------------------------------- 415 */ 416func tsp_abort_yield_smc_entry 417 418 /* 419 * Exceptions masking is already done by the TSPD when entering this 420 * hook so there is no need to do it here. 421 */ 422 423 /* Reset the stack used by the pre-empted SMC */ 424 bl plat_set_my_stack 425 426 /* 427 * Allow some cleanup such as releasing locks. 428 */ 429 bl tsp_abort_smc_handler 430 431 restore_args_call_smc 432 433 /* Should never reach here */ 434 bl plat_panic_handler 435endfunc tsp_abort_yield_smc_entry 436