1/* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <lib/xlat_tables/xlat_tables_defs.h> 13 14 /* 15 * Helper macro to initialise EL3 registers we care about. 16 */ 17 .macro el3_arch_init_common 18 /* --------------------------------------------------------------------- 19 * SCTLR_EL3 has already been initialised - read current value before 20 * modifying. 21 * 22 * SCTLR_EL3.I: Enable the instruction cache. 23 * 24 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault 25 * exception is generated if a load or store instruction executed at 26 * EL3 uses the SP as the base address and the SP is not aligned to a 27 * 16-byte boundary. 28 * 29 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that 30 * load or store one or more registers have an alignment check that the 31 * address being accessed is aligned to the size of the data element(s) 32 * being accessed. 33 * --------------------------------------------------------------------- 34 */ 35 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 36 mrs x0, sctlr_el3 37 orr x0, x0, x1 38 msr sctlr_el3, x0 39 isb 40 41#ifdef IMAGE_BL31 42 /* --------------------------------------------------------------------- 43 * Initialise the per-cpu cache pointer to the CPU. 44 * This is done early to enable crash reporting to have access to crash 45 * stack. Since crash reporting depends on cpu_data to report the 46 * unhandled exception, not doing so can lead to recursive exceptions 47 * due to a NULL TPIDR_EL3. 48 * --------------------------------------------------------------------- 49 */ 50 bl init_cpu_data_ptr 51#endif /* IMAGE_BL31 */ 52 53 /* --------------------------------------------------------------------- 54 * Initialise SCR_EL3, setting all fields rather than relying on hw. 55 * All fields are architecturally UNKNOWN on reset. The following fields 56 * do not change during the TF lifetime. The remaining fields are set to 57 * zero here but are updated ahead of transitioning to a lower EL in the 58 * function cm_init_context_common(). 59 * 60 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 61 * EL2, EL1 and EL0 are not trapped to EL3. 62 * 63 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 64 * EL2, EL1 and EL0 are not trapped to EL3. 65 * 66 * SCR_EL3.SIF: Set to one to disable instruction fetches from 67 * Non-secure memory. 68 * 69 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 70 * both Security states and both Execution states. 71 * 72 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts 73 * to EL3 when executing at any EL. 74 * 75 * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, 76 * disable traps to EL3 when accessing key registers or using pointer 77 * authentication instructions from lower ELs. 78 * --------------------------------------------------------------------- 79 */ 80 mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ 81 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) 82#if CTX_INCLUDE_PAUTH_REGS 83 /* 84 * If the pointer authentication registers are saved during world 85 * switches, enable pointer authentication everywhere, as it is safe to 86 * do so. 87 */ 88 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) 89#endif 90 msr scr_el3, x0 91 92 /* --------------------------------------------------------------------- 93 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 94 * Some fields are architecturally UNKNOWN on reset. 95 * 96 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 97 * Debug exceptions, other than Breakpoint Instruction exceptions, are 98 * disabled from all ELs in Secure state. 99 * 100 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 101 * privileged debug from S-EL1. 102 * 103 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 104 * access to the powerdown debug registers do not trap to EL3. 105 * 106 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 107 * debug registers, other than those registers that are controlled by 108 * MDCR_EL3.TDOSA. 109 * 110 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register 111 * accesses to all Performance Monitors registers do not trap to EL3. 112 * 113 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 114 * prohibited in Secure state. This bit is RES0 in versions of the 115 * architecture earlier than ARMv8.5, setting it to 1 doesn't have any 116 * effect on them. 117 * 118 * MDCR_EL3.SPME: Set to zero so that event counting by the programmable 119 * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2 120 * Debug is not implemented this bit does not have any effect on the 121 * counters unless there is support for the implementation defined 122 * authentication interface ExternalSecureNoninvasiveDebugEnabled(). 123 * --------------------------------------------------------------------- 124 */ 125 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ 126 MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \ 127 ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | MDCR_TDA_BIT | \ 128 MDCR_TPM_BIT)) 129 130 msr mdcr_el3, x0 131 132 /* --------------------------------------------------------------------- 133 * Initialise PMCR_EL0 setting all fields rather than relying 134 * on hw. Some fields are architecturally UNKNOWN on reset. 135 * 136 * PMCR_EL0.LP: Set to one so that event counter overflow, that 137 * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment 138 * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU 139 * is implemented. This bit is RES0 in versions of the architecture 140 * earlier than ARMv8.5, setting it to 1 doesn't have any effect 141 * on them. 142 * 143 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 144 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 145 * that changes PMCCNTR_EL0[63] from 1 to 0. 146 * 147 * PMCR_EL0.DP: Set to one so that the cycle counter, 148 * PMCCNTR_EL0 does not count when event counting is prohibited. 149 * 150 * PMCR_EL0.X: Set to zero to disable export of events. 151 * 152 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 153 * counts on every clock cycle. 154 * --------------------------------------------------------------------- 155 */ 156 mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ 157 PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ 158 ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) 159 160 msr pmcr_el0, x0 161 162 /* --------------------------------------------------------------------- 163 * Enable External Aborts and SError Interrupts now that the exception 164 * vectors have been setup. 165 * --------------------------------------------------------------------- 166 */ 167 msr daifclr, #DAIF_ABT_BIT 168 169 /* --------------------------------------------------------------------- 170 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 171 * All fields are architecturally UNKNOWN on reset. 172 * 173 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, 174 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. 175 * 176 * CPTR_EL3.TTA: Set to zero so that System register accesses to the 177 * trace registers do not trap to EL3. 178 * 179 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 180 * by Advanced SIMD, floating-point or SVE instructions (if implemented) 181 * do not trap to EL3. 182 */ 183 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) 184 msr cptr_el3, x0 185 186 /* 187 * If Data Independent Timing (DIT) functionality is implemented, 188 * always enable DIT in EL3 189 */ 190 mrs x0, id_aa64pfr0_el1 191 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH 192 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED 193 bne 1f 194 mov x0, #DIT_BIT 195 msr DIT, x0 1961: 197 .endm 198 199/* ----------------------------------------------------------------------------- 200 * This is the super set of actions that need to be performed during a cold boot 201 * or a warm boot in EL3. This code is shared by BL1 and BL31. 202 * 203 * This macro will always perform reset handling, architectural initialisations 204 * and stack setup. The rest of the actions are optional because they might not 205 * be needed, depending on the context in which this macro is called. This is 206 * why this macro is parameterised ; each parameter allows to enable/disable 207 * some actions. 208 * 209 * _init_sctlr: 210 * Whether the macro needs to initialise SCTLR_EL3, including configuring 211 * the endianness of data accesses. 212 * 213 * _warm_boot_mailbox: 214 * Whether the macro needs to detect the type of boot (cold/warm). The 215 * detection is based on the platform entrypoint address : if it is zero 216 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 217 * this macro jumps on the platform entrypoint address. 218 * 219 * _secondary_cold_boot: 220 * Whether the macro needs to identify the CPU that is calling it: primary 221 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 222 * the platform initialisations, while the secondaries will be put in a 223 * platform-specific state in the meantime. 224 * 225 * If the caller knows this macro will only be called by the primary CPU 226 * then this parameter can be defined to 0 to skip this step. 227 * 228 * _init_memory: 229 * Whether the macro needs to initialise the memory. 230 * 231 * _init_c_runtime: 232 * Whether the macro needs to initialise the C runtime environment. 233 * 234 * _exception_vectors: 235 * Address of the exception vectors to program in the VBAR_EL3 register. 236 * 237 * _pie_fixup_size: 238 * Size of memory region to fixup Global Descriptor Table (GDT). 239 * 240 * A non-zero value is expected when firmware needs GDT to be fixed-up. 241 * 242 * ----------------------------------------------------------------------------- 243 */ 244 .macro el3_entrypoint_common \ 245 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 246 _init_memory, _init_c_runtime, _exception_vectors, \ 247 _pie_fixup_size 248 249 .if \_init_sctlr 250 /* ------------------------------------------------------------- 251 * This is the initialisation of SCTLR_EL3 and so must ensure 252 * that all fields are explicitly set rather than relying on hw. 253 * Some fields reset to an IMPLEMENTATION DEFINED value and 254 * others are architecturally UNKNOWN on reset. 255 * 256 * SCTLR.EE: Set the CPU endianness before doing anything that 257 * might involve memory reads or writes. Set to zero to select 258 * Little Endian. 259 * 260 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can 261 * force all memory regions that are writeable to be treated as 262 * XN (Execute-never). Set to zero so that this control has no 263 * effect on memory access permissions. 264 * 265 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. 266 * 267 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. 268 * 269 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 270 * safe behaviour upon exception entry to EL3. 271 * ------------------------------------------------------------- 272 */ 273 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ 274 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) 275 msr sctlr_el3, x0 276 isb 277 .endif /* _init_sctlr */ 278 279 .if \_warm_boot_mailbox 280 /* ------------------------------------------------------------- 281 * This code will be executed for both warm and cold resets. 282 * Now is the time to distinguish between the two. 283 * Query the platform entrypoint address and if it is not zero 284 * then it means it is a warm boot so jump to this address. 285 * ------------------------------------------------------------- 286 */ 287 bl plat_get_my_entrypoint 288 cbz x0, do_cold_boot 289 br x0 290 291 do_cold_boot: 292 .endif /* _warm_boot_mailbox */ 293 294 .if \_pie_fixup_size 295#if ENABLE_PIE 296 /* 297 * ------------------------------------------------------------ 298 * If PIE is enabled fixup the Global descriptor Table only 299 * once during primary core cold boot path. 300 * 301 * Compile time base address, required for fixup, is calculated 302 * using "pie_fixup" label present within first page. 303 * ------------------------------------------------------------ 304 */ 305 pie_fixup: 306 ldr x0, =pie_fixup 307 and x0, x0, #~(PAGE_SIZE - 1) 308 mov_imm x1, \_pie_fixup_size 309 add x1, x1, x0 310 bl fixup_gdt_reloc 311#endif /* ENABLE_PIE */ 312 .endif /* _pie_fixup_size */ 313 314 /* --------------------------------------------------------------------- 315 * Set the exception vectors. 316 * --------------------------------------------------------------------- 317 */ 318 adr x0, \_exception_vectors 319 msr vbar_el3, x0 320 isb 321 322 /* --------------------------------------------------------------------- 323 * It is a cold boot. 324 * Perform any processor specific actions upon reset e.g. cache, TLB 325 * invalidations etc. 326 * --------------------------------------------------------------------- 327 */ 328 bl reset_handler 329 330 el3_arch_init_common 331 332 .if \_secondary_cold_boot 333 /* ------------------------------------------------------------- 334 * Check if this is a primary or secondary CPU cold boot. 335 * The primary CPU will set up the platform while the 336 * secondaries are placed in a platform-specific state until the 337 * primary CPU performs the necessary actions to bring them out 338 * of that state and allows entry into the OS. 339 * ------------------------------------------------------------- 340 */ 341 bl plat_is_my_cpu_primary 342 cbnz w0, do_primary_cold_boot 343 344 /* This is a cold boot on a secondary CPU */ 345 bl plat_secondary_cold_boot_setup 346 /* plat_secondary_cold_boot_setup() is not supposed to return */ 347 bl el3_panic 348 349 do_primary_cold_boot: 350 .endif /* _secondary_cold_boot */ 351 352 /* --------------------------------------------------------------------- 353 * Initialize memory now. Secondary CPU initialization won't get to this 354 * point. 355 * --------------------------------------------------------------------- 356 */ 357 358 .if \_init_memory 359 bl platform_mem_init 360 .endif /* _init_memory */ 361 362 /* --------------------------------------------------------------------- 363 * Init C runtime environment: 364 * - Zero-initialise the NOBITS sections. There are 2 of them: 365 * - the .bss section; 366 * - the coherent memory section (if any). 367 * - Relocate the data section from ROM to RAM, if required. 368 * --------------------------------------------------------------------- 369 */ 370 .if \_init_c_runtime 371#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE) 372 /* ------------------------------------------------------------- 373 * Invalidate the RW memory used by the BL31 image. This 374 * includes the data and NOBITS sections. This is done to 375 * safeguard against possible corruption of this memory by 376 * dirty cache lines in a system cache as a result of use by 377 * an earlier boot loader stage. 378 * ------------------------------------------------------------- 379 */ 380 adrp x0, __RW_START__ 381 add x0, x0, :lo12:__RW_START__ 382 adrp x1, __RW_END__ 383 add x1, x1, :lo12:__RW_END__ 384 sub x1, x1, x0 385 bl inv_dcache_range 386#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION 387 adrp x0, __NOBITS_START__ 388 add x0, x0, :lo12:__NOBITS_START__ 389 adrp x1, __NOBITS_END__ 390 add x1, x1, :lo12:__NOBITS_END__ 391 sub x1, x1, x0 392 bl inv_dcache_range 393#endif 394#endif 395 adrp x0, __BSS_START__ 396 add x0, x0, :lo12:__BSS_START__ 397 398 adrp x1, __BSS_END__ 399 add x1, x1, :lo12:__BSS_END__ 400 sub x1, x1, x0 401 bl zeromem 402 403#if USE_COHERENT_MEM 404 adrp x0, __COHERENT_RAM_START__ 405 add x0, x0, :lo12:__COHERENT_RAM_START__ 406 adrp x1, __COHERENT_RAM_END_UNALIGNED__ 407 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ 408 sub x1, x1, x0 409 bl zeromem 410#endif 411 412#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) 413 adrp x0, __DATA_RAM_START__ 414 add x0, x0, :lo12:__DATA_RAM_START__ 415 adrp x1, __DATA_ROM_START__ 416 add x1, x1, :lo12:__DATA_ROM_START__ 417 adrp x2, __DATA_RAM_END__ 418 add x2, x2, :lo12:__DATA_RAM_END__ 419 sub x2, x2, x0 420 bl memcpy16 421#endif 422 .endif /* _init_c_runtime */ 423 424 /* --------------------------------------------------------------------- 425 * Use SP_EL0 for the C runtime stack. 426 * --------------------------------------------------------------------- 427 */ 428 msr spsel, #0 429 430 /* --------------------------------------------------------------------- 431 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 432 * the MMU is enabled. There is no risk of reading stale stack memory 433 * after enabling the MMU as only the primary CPU is running at the 434 * moment. 435 * --------------------------------------------------------------------- 436 */ 437 bl plat_set_my_stack 438 439#if STACK_PROTECTOR_ENABLED 440 .if \_init_c_runtime 441 bl update_stack_protector_canary 442 .endif /* _init_c_runtime */ 443#endif 444 .endm 445 446#endif /* EL3_COMMON_MACROS_S */ 447