1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <memctrl_v2.h> 10#include <plat/common/common_def.h> 11#include <tegra_def.h> 12 13#define TEGRA186_STATE_SYSTEM_SUSPEND 0x5C7 14#define TEGRA186_STATE_SYSTEM_RESUME 0x600D 15#define TEGRA186_SMMU_CTX_SIZE 0x420 16 17 .globl tegra186_cpu_reset_handler 18 19/* CPU reset handler routine */ 20func tegra186_cpu_reset_handler _align=4 21 /* check if we are exiting system suspend state */ 22 adr x0, __tegra186_system_suspend_state 23 ldr x1, [x0] 24 mov x2, #TEGRA186_STATE_SYSTEM_SUSPEND 25 lsl x2, x2, #16 26 add x2, x2, #TEGRA186_STATE_SYSTEM_SUSPEND 27 cmp x1, x2 28 bne boot_cpu 29 30 /* set system resume state */ 31 mov x1, #TEGRA186_STATE_SYSTEM_RESUME 32 lsl x1, x1, #16 33 mov x2, #TEGRA186_STATE_SYSTEM_RESUME 34 add x1, x1, x2 35 str x1, [x0] 36 dsb sy 37 38 /* prepare to relocate to TZSRAM */ 39 mov x0, #BL31_BASE 40 adr x1, __tegra186_cpu_reset_handler_end 41 adr x2, __tegra186_cpu_reset_handler_data 42 ldr x2, [x2, #8] 43 44 /* memcpy16 */ 45m_loop16: 46 cmp x2, #16 47 b.lt m_loop1 48 ldp x3, x4, [x1], #16 49 stp x3, x4, [x0], #16 50 sub x2, x2, #16 51 b m_loop16 52 /* copy byte per byte */ 53m_loop1: 54 cbz x2, boot_cpu 55 ldrb w3, [x1], #1 56 strb w3, [x0], #1 57 subs x2, x2, #1 58 b.ne m_loop1 59 60boot_cpu: 61 adr x0, __tegra186_cpu_reset_handler_data 62 ldr x0, [x0] 63 br x0 64endfunc tegra186_cpu_reset_handler 65 66 /* 67 * Tegra186 reset data (offset 0x0 - 0x430) 68 * 69 * 0x000: secure world's entrypoint 70 * 0x008: BL31 size (RO + RW) 71 * 0x00C: SMMU context start 72 * 0x42C: SMMU context end 73 */ 74 75 .align 4 76 .type __tegra186_cpu_reset_handler_data, %object 77 .globl __tegra186_cpu_reset_handler_data 78__tegra186_cpu_reset_handler_data: 79 .quad tegra_secure_entrypoint 80 .quad __BL31_END__ - BL31_BASE 81 82 .globl __tegra186_system_suspend_state 83__tegra186_system_suspend_state: 84 .quad 0 85 86 .align 4 87 .globl __tegra186_smmu_context 88__tegra186_smmu_context: 89 .rept TEGRA186_SMMU_CTX_SIZE 90 .quad 0 91 .endr 92 .size __tegra186_cpu_reset_handler_data, \ 93 . - __tegra186_cpu_reset_handler_data 94 95 .align 4 96 .globl __tegra186_cpu_reset_handler_end 97__tegra186_cpu_reset_handler_end: 98 99 .globl tegra186_get_cpu_reset_handler_size 100 .globl tegra186_get_cpu_reset_handler_base 101 .globl tegra186_get_smmu_ctx_offset 102 .globl tegra186_set_system_suspend_entry 103 104/* return size of the CPU reset handler */ 105func tegra186_get_cpu_reset_handler_size 106 adr x0, __tegra186_cpu_reset_handler_end 107 adr x1, tegra186_cpu_reset_handler 108 sub x0, x0, x1 109 ret 110endfunc tegra186_get_cpu_reset_handler_size 111 112/* return the start address of the CPU reset handler */ 113func tegra186_get_cpu_reset_handler_base 114 adr x0, tegra186_cpu_reset_handler 115 ret 116endfunc tegra186_get_cpu_reset_handler_base 117 118/* return the size of the SMMU context */ 119func tegra186_get_smmu_ctx_offset 120 adr x0, __tegra186_smmu_context 121 adr x1, tegra186_cpu_reset_handler 122 sub x0, x0, x1 123 ret 124endfunc tegra186_get_smmu_ctx_offset 125 126/* set system suspend state before SC7 entry */ 127func tegra186_set_system_suspend_entry 128 mov x0, #TEGRA_MC_BASE 129 mov x3, #MC_SECURITY_CFG3_0 130 ldr w1, [x0, x3] 131 lsl x1, x1, #32 132 mov x3, #MC_SECURITY_CFG0_0 133 ldr w2, [x0, x3] 134 orr x3, x1, x2 /* TZDRAM base */ 135 adr x0, __tegra186_system_suspend_state 136 adr x1, tegra186_cpu_reset_handler 137 sub x2, x0, x1 /* offset in TZDRAM */ 138 mov x0, #TEGRA186_STATE_SYSTEM_SUSPEND 139 lsl x0, x0, #16 140 add x0, x0, #TEGRA186_STATE_SYSTEM_SUSPEND 141 str x0, [x3, x2] /* set value in TZDRAM */ 142 dsb sy 143 ret 144endfunc tegra186_set_system_suspend_entry 145