1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <lib/debugfs.h> 15 #include <lib/extensions/ras.h> 16 #include <lib/mmio.h> 17 #include <lib/xlat_tables/xlat_tables_compat.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 22 /* 23 * Placeholder variables for copying the arguments that have been passed to 24 * BL31 from BL2. 25 */ 26 static entry_point_info_t bl32_image_ep_info; 27 static entry_point_info_t bl33_image_ep_info; 28 29 #if !RESET_TO_BL31 30 /* 31 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 32 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 33 */ 34 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 35 #endif 36 37 /* Weak definitions may be overridden in specific ARM standard platform */ 38 #pragma weak bl31_early_platform_setup2 39 #pragma weak bl31_platform_setup 40 #pragma weak bl31_plat_arch_setup 41 #pragma weak bl31_plat_get_next_image_ep_info 42 43 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 44 BL31_START, \ 45 BL31_END - BL31_START, \ 46 MT_MEMORY | MT_RW | MT_SECURE) 47 #if RECLAIM_INIT_CODE 48 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 49 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_INIT_CODE_END); 50 51 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 52 BL_INIT_CODE_BASE, \ 53 BL_INIT_CODE_END \ 54 - BL_INIT_CODE_BASE, \ 55 MT_CODE | MT_SECURE) 56 #endif 57 58 #if SEPARATE_NOBITS_REGION 59 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 60 BL31_NOBITS_BASE, \ 61 BL31_NOBITS_LIMIT \ 62 - BL31_NOBITS_BASE, \ 63 MT_MEMORY | MT_RW | MT_SECURE) 64 65 #endif 66 /******************************************************************************* 67 * Return a pointer to the 'entry_point_info' structure of the next image for the 68 * security state specified. BL33 corresponds to the non-secure image type 69 * while BL32 corresponds to the secure image type. A NULL pointer is returned 70 * if the image does not exist. 71 ******************************************************************************/ 72 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 73 { 74 entry_point_info_t *next_image_info; 75 76 assert(sec_state_is_valid(type)); 77 next_image_info = (type == NON_SECURE) 78 ? &bl33_image_ep_info : &bl32_image_ep_info; 79 /* 80 * None of the images on the ARM development platforms can have 0x0 81 * as the entrypoint 82 */ 83 if (next_image_info->pc) 84 return next_image_info; 85 else 86 return NULL; 87 } 88 89 /******************************************************************************* 90 * Perform any BL31 early platform setup common to ARM standard platforms. 91 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 92 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 93 * done before the MMU is initialized so that the memory layout can be used 94 * while creating page tables. BL2 has flushed this information to memory, so 95 * we are guaranteed to pick up good data. 96 ******************************************************************************/ 97 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 98 uintptr_t hw_config, void *plat_params_from_bl2) 99 { 100 /* Initialize the console to provide early debug support */ 101 arm_console_boot_init(); 102 103 #if RESET_TO_BL31 104 /* There are no parameters from BL2 if BL31 is a reset vector */ 105 assert(from_bl2 == NULL); 106 assert(plat_params_from_bl2 == NULL); 107 108 # ifdef BL32_BASE 109 /* Populate entry point information for BL32 */ 110 SET_PARAM_HEAD(&bl32_image_ep_info, 111 PARAM_EP, 112 VERSION_1, 113 0); 114 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 115 bl32_image_ep_info.pc = BL32_BASE; 116 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 117 # endif /* BL32_BASE */ 118 119 /* Populate entry point information for BL33 */ 120 SET_PARAM_HEAD(&bl33_image_ep_info, 121 PARAM_EP, 122 VERSION_1, 123 0); 124 /* 125 * Tell BL31 where the non-trusted software image 126 * is located and the entry state information 127 */ 128 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 129 130 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 131 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 132 133 # if ARM_LINUX_KERNEL_AS_BL33 134 /* 135 * According to the file ``Documentation/arm64/booting.txt`` of the 136 * Linux kernel tree, Linux expects the physical address of the device 137 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 138 * must be 0. 139 */ 140 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 141 bl33_image_ep_info.args.arg1 = 0U; 142 bl33_image_ep_info.args.arg2 = 0U; 143 bl33_image_ep_info.args.arg3 = 0U; 144 # endif 145 146 #else /* RESET_TO_BL31 */ 147 148 /* 149 * In debug builds, we pass a special value in 'plat_params_from_bl2' 150 * to verify platform parameters from BL2 to BL31. 151 * In release builds, it's not used. 152 */ 153 assert(((unsigned long long)plat_params_from_bl2) == 154 ARM_BL31_PLAT_PARAM_VAL); 155 156 /* 157 * Check params passed from BL2 should not be NULL, 158 */ 159 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 160 assert(params_from_bl2 != NULL); 161 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 162 assert(params_from_bl2->h.version >= VERSION_2); 163 164 bl_params_node_t *bl_params = params_from_bl2->head; 165 166 /* 167 * Copy BL33 and BL32 (if present), entry point information. 168 * They are stored in Secure RAM, in BL2's address space. 169 */ 170 while (bl_params != NULL) { 171 if (bl_params->image_id == BL32_IMAGE_ID) 172 bl32_image_ep_info = *bl_params->ep_info; 173 174 if (bl_params->image_id == BL33_IMAGE_ID) 175 bl33_image_ep_info = *bl_params->ep_info; 176 177 bl_params = bl_params->next_params_info; 178 } 179 180 if (bl33_image_ep_info.pc == 0U) 181 panic(); 182 #endif /* RESET_TO_BL31 */ 183 } 184 185 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 186 u_register_t arg2, u_register_t arg3) 187 { 188 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 189 190 /* 191 * Initialize Interconnect for this cluster during cold boot. 192 * No need for locks as no other CPU is active. 193 */ 194 plat_arm_interconnect_init(); 195 196 /* 197 * Enable Interconnect coherency for the primary CPU's cluster. 198 * Earlier bootloader stages might already do this (e.g. Trusted 199 * Firmware's BL1 does it) but we can't assume so. There is no harm in 200 * executing this code twice anyway. 201 * Platform specific PSCI code will enable coherency for other 202 * clusters. 203 */ 204 plat_arm_interconnect_enter_coherency(); 205 } 206 207 /******************************************************************************* 208 * Perform any BL31 platform setup common to ARM standard platforms 209 ******************************************************************************/ 210 void arm_bl31_platform_setup(void) 211 { 212 /* Initialize the GIC driver, cpu and distributor interfaces */ 213 plat_arm_gic_driver_init(); 214 plat_arm_gic_init(); 215 216 #if RESET_TO_BL31 217 /* 218 * Do initial security configuration to allow DRAM/device access 219 * (if earlier BL has not already done so). 220 */ 221 plat_arm_security_setup(); 222 223 #if defined(PLAT_ARM_MEM_PROT_ADDR) 224 arm_nor_psci_do_dyn_mem_protect(); 225 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 226 227 #endif /* RESET_TO_BL31 */ 228 229 /* Enable and initialize the System level generic timer */ 230 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 231 CNTCR_FCREQ(0U) | CNTCR_EN); 232 233 /* Allow access to the System counter timer module */ 234 arm_configure_sys_timer(); 235 236 /* Initialize power controller before setting up topology */ 237 plat_arm_pwrc_setup(); 238 239 #if RAS_EXTENSION 240 ras_init(); 241 #endif 242 243 #if USE_DEBUGFS 244 debugfs_init(); 245 #endif /* USE_DEBUGFS */ 246 } 247 248 /******************************************************************************* 249 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 250 * standard platforms 251 * Perform BL31 platform setup 252 ******************************************************************************/ 253 void arm_bl31_plat_runtime_setup(void) 254 { 255 console_switch_state(CONSOLE_FLAG_RUNTIME); 256 257 /* Initialize the runtime console */ 258 arm_console_runtime_init(); 259 260 #if RECLAIM_INIT_CODE 261 arm_free_init_memory(); 262 #endif 263 264 #if PLAT_RO_XLAT_TABLES 265 arm_xlat_make_tables_readonly(); 266 #endif 267 } 268 269 #if RECLAIM_INIT_CODE 270 /* 271 * Zero out and make RW memory used to store image boot time code so it can 272 * be reclaimed during runtime 273 */ 274 void arm_free_init_memory(void) 275 { 276 int ret = xlat_change_mem_attributes(BL_INIT_CODE_BASE, 277 BL_INIT_CODE_END - BL_INIT_CODE_BASE, 278 MT_RW_DATA); 279 280 if (ret != 0) { 281 ERROR("Could not reclaim initialization code"); 282 panic(); 283 } 284 } 285 #endif 286 287 void __init bl31_platform_setup(void) 288 { 289 arm_bl31_platform_setup(); 290 } 291 292 void bl31_plat_runtime_setup(void) 293 { 294 arm_bl31_plat_runtime_setup(); 295 } 296 297 /******************************************************************************* 298 * Perform the very early platform specific architectural setup shared between 299 * ARM standard platforms. This only does basic initialization. Later 300 * architectural setup (bl31_arch_setup()) does not do anything platform 301 * specific. 302 ******************************************************************************/ 303 void __init arm_bl31_plat_arch_setup(void) 304 { 305 const mmap_region_t bl_regions[] = { 306 MAP_BL31_TOTAL, 307 #if RECLAIM_INIT_CODE 308 MAP_BL_INIT_CODE, 309 #endif 310 #if SEPARATE_NOBITS_REGION 311 MAP_BL31_NOBITS, 312 #endif 313 ARM_MAP_BL_RO, 314 #if USE_ROMLIB 315 ARM_MAP_ROMLIB_CODE, 316 ARM_MAP_ROMLIB_DATA, 317 #endif 318 #if USE_COHERENT_MEM 319 ARM_MAP_BL_COHERENT_RAM, 320 #endif 321 {0} 322 }; 323 324 setup_page_tables(bl_regions, plat_arm_get_mmap()); 325 326 enable_mmu_el3(0); 327 328 arm_setup_romlib(); 329 } 330 331 void __init bl31_plat_arch_setup(void) 332 { 333 arm_bl31_plat_arch_setup(); 334 } 335