xref: /rk3399_ARM-atf/fdts/stm32mp157a-dk1.dts (revision cf6c30e08ba54a22a0ce8abd6eac8b1d1ccad324)
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2018-2019 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@st.com>.
5 */
6
7/dts-v1/;
8
9#include "stm32mp157c.dtsi"
10#include "stm32mp157cac-pinctrl.dtsi"
11
12/ {
13	model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
14	compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
15
16	aliases {
17		serial0 = &uart4;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24};
25
26&clk_hse {
27	st,digbypass;
28};
29
30&i2c4 {
31	pinctrl-names = "default";
32	pinctrl-0 = <&i2c4_pins_a>;
33	i2c-scl-rising-time-ns = <185>;
34	i2c-scl-falling-time-ns = <20>;
35	status = "okay";
36
37	pmic: stpmic@33 {
38		compatible = "st,stpmic1";
39		reg = <0x33>;
40		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
41		interrupt-controller;
42		#interrupt-cells = <2>;
43		status = "okay";
44
45		st,main-control-register = <0x04>;
46		st,vin-control-register = <0xc0>;
47		st,usb-control-register = <0x20>;
48
49		regulators {
50			compatible = "st,stpmic1-regulators";
51
52			ldo1-supply = <&v3v3>;
53			ldo3-supply = <&vdd_ddr>;
54			ldo6-supply = <&v3v3>;
55
56			vddcore: buck1 {
57				regulator-name = "vddcore";
58				regulator-min-microvolt = <1200000>;
59				regulator-max-microvolt = <1350000>;
60				regulator-always-on;
61				regulator-initial-mode = <0>;
62				regulator-over-current-protection;
63			};
64
65			vdd_ddr: buck2 {
66				regulator-name = "vdd_ddr";
67				regulator-min-microvolt = <1350000>;
68				regulator-max-microvolt = <1350000>;
69				regulator-always-on;
70				regulator-initial-mode = <0>;
71				regulator-over-current-protection;
72			};
73
74			vdd: buck3 {
75				regulator-name = "vdd";
76				regulator-min-microvolt = <3300000>;
77				regulator-max-microvolt = <3300000>;
78				regulator-always-on;
79				st,mask-reset;
80				regulator-initial-mode = <0>;
81				regulator-over-current-protection;
82			};
83
84			v3v3: buck4 {
85				regulator-name = "v3v3";
86				regulator-min-microvolt = <3300000>;
87				regulator-max-microvolt = <3300000>;
88				regulator-always-on;
89				regulator-over-current-protection;
90				regulator-initial-mode = <0>;
91			};
92
93			v1v8_audio: ldo1 {
94				regulator-name = "v1v8_audio";
95				regulator-min-microvolt = <1800000>;
96				regulator-max-microvolt = <1800000>;
97				regulator-always-on;
98			};
99
100			v3v3_hdmi: ldo2 {
101				regulator-name = "v3v3_hdmi";
102				regulator-min-microvolt = <3300000>;
103				regulator-max-microvolt = <3300000>;
104				regulator-always-on;
105			};
106
107			vtt_ddr: ldo3 {
108				regulator-name = "vtt_ddr";
109				regulator-min-microvolt = <500000>;
110				regulator-max-microvolt = <750000>;
111				regulator-always-on;
112				regulator-over-current-protection;
113			};
114
115			vdd_usb: ldo4 {
116				regulator-name = "vdd_usb";
117				regulator-min-microvolt = <3300000>;
118				regulator-max-microvolt = <3300000>;
119			};
120
121			vdda: ldo5 {
122				regulator-name = "vdda";
123				regulator-min-microvolt = <2900000>;
124				regulator-max-microvolt = <2900000>;
125				regulator-boot-on;
126			};
127
128			v1v2_hdmi: ldo6 {
129				regulator-name = "v1v2_hdmi";
130				regulator-min-microvolt = <1200000>;
131				regulator-max-microvolt = <1200000>;
132				regulator-always-on;
133			};
134
135			vref_ddr: vref_ddr {
136				regulator-name = "vref_ddr";
137				regulator-always-on;
138				regulator-over-current-protection;
139			};
140		};
141	};
142};
143
144&iwdg2 {
145	timeout-sec = <32>;
146	status = "okay";
147};
148
149&rng1 {
150	status = "okay";
151};
152
153&rtc {
154	status = "okay";
155};
156
157&sdmmc1 {
158	pinctrl-names = "default";
159	pinctrl-0 = <&sdmmc1_b4_pins_a>;
160	broken-cd;
161	st,neg-edge;
162	bus-width = <4>;
163	vmmc-supply = <&v3v3>;
164	status = "okay";
165};
166
167&uart4 {
168	pinctrl-names = "default";
169	pinctrl-0 = <&uart4_pins_a>;
170	status = "okay";
171};
172
173/* ATF Specific */
174#include <dt-bindings/clock/stm32mp1-clksrc.h>
175#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
176
177/ {
178	aliases {
179		gpio0 = &gpioa;
180		gpio1 = &gpiob;
181		gpio2 = &gpioc;
182		gpio3 = &gpiod;
183		gpio4 = &gpioe;
184		gpio5 = &gpiof;
185		gpio6 = &gpiog;
186		gpio7 = &gpioh;
187		gpio8 = &gpioi;
188		gpio25 = &gpioz;
189		i2c3 = &i2c4;
190	};
191
192	soc {
193		stgen: stgen@5C008000 {
194			compatible = "st,stm32-stgen";
195			reg = <0x5C008000 0x1000>;
196			status = "okay";
197		};
198	};
199};
200
201/* CLOCK init */
202&rcc {
203	secure-status = "disabled";
204	st,clksrc = <
205		CLK_MPU_PLL1P
206		CLK_AXI_PLL2P
207		CLK_MCU_PLL3P
208		CLK_PLL12_HSE
209		CLK_PLL3_HSE
210		CLK_PLL4_HSE
211		CLK_RTC_LSE
212		CLK_MCO1_DISABLED
213		CLK_MCO2_DISABLED
214	>;
215
216	st,clkdiv = <
217		1 /*MPU*/
218		0 /*AXI*/
219		0 /*MCU*/
220		1 /*APB1*/
221		1 /*APB2*/
222		1 /*APB3*/
223		1 /*APB4*/
224		2 /*APB5*/
225		23 /*RTC*/
226		0 /*MCO1*/
227		0 /*MCO2*/
228	>;
229
230	st,pkcs = <
231		CLK_CKPER_HSE
232		CLK_FMC_ACLK
233		CLK_QSPI_ACLK
234		CLK_ETH_DISABLED
235		CLK_SDMMC12_PLL4P
236		CLK_DSI_DSIPLL
237		CLK_STGEN_HSE
238		CLK_USBPHY_HSE
239		CLK_SPI2S1_PLL3Q
240		CLK_SPI2S23_PLL3Q
241		CLK_SPI45_HSI
242		CLK_SPI6_HSI
243		CLK_I2C46_HSI
244		CLK_SDMMC3_PLL4P
245		CLK_USBO_USBPHY
246		CLK_ADC_CKPER
247		CLK_CEC_LSE
248		CLK_I2C12_HSI
249		CLK_I2C35_HSI
250		CLK_UART1_HSI
251		CLK_UART24_HSI
252		CLK_UART35_HSI
253		CLK_UART6_HSI
254		CLK_UART78_HSI
255		CLK_SPDIF_PLL4P
256		CLK_FDCAN_PLL4Q
257		CLK_SAI1_PLL3Q
258		CLK_SAI2_PLL3Q
259		CLK_SAI3_PLL3Q
260		CLK_SAI4_PLL3Q
261		CLK_RNG1_LSI
262		CLK_RNG2_LSI
263		CLK_LPTIM1_PCLK1
264		CLK_LPTIM23_PCLK3
265		CLK_LPTIM45_LSE
266	>;
267
268	/* VCO = 1300.0 MHz => P = 650 (CPU) */
269	pll1: st,pll@0 {
270		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
271		frac = < 0x800 >;
272	};
273
274	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
275	pll2: st,pll@1 {
276		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
277		frac = < 0x1400 >;
278	};
279
280	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
281	pll3: st,pll@2 {
282		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
283		frac = < 0x1a04 >;
284	};
285
286	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
287	pll4: st,pll@3 {
288		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
289	};
290};
291