1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <lib/el3_runtime/context_mgmt.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables.h> 21 #include <plat/common/platform.h> 22 23 #include <gpc.h> 24 #include <imx_uart.h> 25 #include <plat_imx8.h> 26 27 IMPORT_SYM(uintptr_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START); 28 IMPORT_SYM(uintptr_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END); 29 IMPORT_SYM(uintptr_t, __RO_START__, BL31_RO_START); 30 IMPORT_SYM(uintptr_t, __RO_END__, BL31_RO_END); 31 IMPORT_SYM(uintptr_t, __RW_START__, BL31_RW_START); 32 IMPORT_SYM(uintptr_t, __RW_END__, BL31_RW_END); 33 34 static const mmap_region_t imx_mmap[] = { 35 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */ 36 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 37 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */ 38 {0}, 39 }; 40 41 static entry_point_info_t bl32_image_ep_info; 42 static entry_point_info_t bl33_image_ep_info; 43 44 /* get SPSR for BL33 entry */ 45 static uint32_t get_spsr_for_bl33_entry(void) 46 { 47 unsigned long el_status; 48 unsigned long mode; 49 uint32_t spsr; 50 51 /* figure out what mode we enter the non-secure world */ 52 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 53 el_status &= ID_AA64PFR0_ELX_MASK; 54 55 mode = (el_status) ? MODE_EL2 : MODE_EL1; 56 57 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 58 return spsr; 59 } 60 61 static void bl31_tz380_setup(void) 62 { 63 unsigned int val; 64 65 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); 66 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 67 return; 68 69 tzc380_init(IMX_TZASC_BASE); 70 /* 71 * Need to substact offset 0x40000000 from CPU address when 72 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW 73 */ 74 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 75 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 76 } 77 78 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 79 u_register_t arg2, u_register_t arg3) 80 { 81 int i; 82 /* enable CSU NS access permission */ 83 for (i = 0; i < 64; i++) { 84 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); 85 } 86 87 /* config CAAM JRaMID set MID to Cortex A */ 88 mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); 89 mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); 90 mmio_write_32(CAAM_JR2MID, CAAM_NS_MID); 91 92 #if DEBUG_CONSOLE 93 static console_uart_t console; 94 95 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 96 IMX_CONSOLE_BAUDRATE, &console); 97 #endif 98 /* 99 * tell BL3-1 where the non-secure software image is located 100 * and the entry state information. 101 */ 102 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 103 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 104 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 105 106 bl31_tz380_setup(); 107 } 108 109 void bl31_plat_arch_setup(void) 110 { 111 mmap_add_region(BL31_RO_START, BL31_RO_START, (BL31_RO_END - BL31_RO_START), 112 MT_MEMORY | MT_RO | MT_SECURE); 113 mmap_add_region(BL31_RW_START, BL31_RW_START, (BL31_RW_END - BL31_RW_START), 114 MT_MEMORY | MT_RW | MT_SECURE); 115 116 mmap_add(imx_mmap); 117 118 #if USE_COHERENT_MEM 119 mmap_add_region(BL31_COHERENT_RAM_START, BL31_COHERENT_RAM_START, 120 BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START, 121 MT_DEVICE | MT_RW | MT_SECURE); 122 #endif 123 /* setup xlat table */ 124 init_xlat_tables(); 125 /* enable the MMU */ 126 enable_mmu_el3(0); 127 } 128 129 void bl31_platform_setup(void) 130 { 131 /* init the GICv3 cpu and distributor interface */ 132 plat_gic_driver_init(); 133 plat_gic_init(); 134 135 /* gpc init */ 136 imx_gpc_init(); 137 } 138 139 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 140 { 141 if (type == NON_SECURE) 142 return &bl33_image_ep_info; 143 if (type == SECURE) 144 return &bl32_image_ep_info; 145 146 return NULL; 147 } 148 149 unsigned int plat_get_syscnt_freq2(void) 150 { 151 return COUNTER_FREQUENCY; 152 } 153 154 void bl31_plat_runtime_setup(void) 155 { 156 return; 157 } 158