xref: /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/platform_t186.mk (revision 04e06973e1fef87849c498c7f045aa2be8aada1c)
1#
2# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8# platform configs
9ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS	:= 1
10$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
11
12ENABLE_CHIP_VERIFICATION_HARNESS	:= 0
13$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS))
14
15RESET_TO_BL31				:= 1
16
17PROGRAMMABLE_RESET_ADDRESS		:= 0
18
19COLD_BOOT_SINGLE_CPU			:= 1
20
21RELOCATE_BL32_IMAGE			:= 1
22
23# platform settings
24TZDRAM_BASE				:= 0x30000000
25$(eval $(call add_define,TZDRAM_BASE))
26
27PLATFORM_CLUSTER_COUNT			:= 2
28$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
29
30PLATFORM_MAX_CPUS_PER_CLUSTER		:= 4
31$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
32
33MAX_XLAT_TABLES				:= 25
34$(eval $(call add_define,MAX_XLAT_TABLES))
35
36MAX_MMAP_REGIONS			:= 30
37$(eval $(call add_define,MAX_MMAP_REGIONS))
38
39# platform files
40PLAT_INCLUDES		+=	-Iplat/nvidia/tegra/include/t186 \
41				-I${SOC_DIR}/drivers/include
42
43BL31_SOURCES		+=	drivers/ti/uart/aarch64/16550_console.S	\
44				lib/cpus/aarch64/denver.S		\
45				lib/cpus/aarch64/cortex_a57.S		\
46				${COMMON_DIR}/drivers/bpmp_ipc/intf.c   \
47				${COMMON_DIR}/drivers/bpmp_ipc/ivc.c    \
48				${COMMON_DIR}/drivers/gpcdma/gpcdma.c	\
49				${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
50				${COMMON_DIR}/drivers/smmu/smmu.c	\
51				${SOC_DIR}/drivers/mce/mce.c		\
52				${SOC_DIR}/drivers/mce/ari.c		\
53				${SOC_DIR}/drivers/mce/nvg.c		\
54				${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
55				$(SOC_DIR)/drivers/se/se.c \
56				${SOC_DIR}/plat_memctrl.c		\
57				${SOC_DIR}/plat_psci_handlers.c		\
58				${SOC_DIR}/plat_setup.c			\
59				${SOC_DIR}/plat_secondary.c		\
60				${SOC_DIR}/plat_sip_calls.c		\
61				${SOC_DIR}/plat_smmu.c			\
62				${SOC_DIR}/plat_trampoline.S
63
64# Enable workarounds for selected Cortex-A57 erratas.
65A57_DISABLE_NON_TEMPORAL_HINT	:=	1
66ERRATA_A57_806969		:=	1
67ERRATA_A57_813419		:=	1
68ERRATA_A57_813420		:=	1
69ERRATA_A57_826974		:=	1
70ERRATA_A57_826977		:=	1
71ERRATA_A57_828024		:=	1
72ERRATA_A57_829520		:=	1
73ERRATA_A57_833471		:=	1
74
75# Enable higher performance Non-cacheable load forwarding
76A57_ENABLE_NONCACHEABLE_LOAD_FWD	:=	1
77