1Trusted Firmware-A Porting Guide 2================================ 3 4 5.. section-numbering:: 6 :suffix: . 7 8.. contents:: 9 10-------------- 11 12Introduction 13------------ 14 15Porting Trusted Firmware-A (TF-A) to a new platform involves making some 16mandatory and optional modifications for both the cold and warm boot paths. 17Modifications consist of: 18 19- Implementing a platform-specific function or variable, 20- Setting up the execution context in a certain way, or 21- Defining certain constants (for example #defines). 22 23The platform-specific functions and variables are declared in 24`include/plat/common/platform.h`_. The firmware provides a default implementation 25of variables and functions to fulfill the optional requirements. These 26implementations are all weakly defined; they are provided to ease the porting 27effort. Each platform port can override them with its own implementation if the 28default implementation is inadequate. 29 30Some modifications are common to all Boot Loader (BL) stages. Section 2 31discusses these in detail. The subsequent sections discuss the remaining 32modifications for each BL stage in detail. 33 34This document should be read in conjunction with the TF-A `User Guide`_. 35 36Please refer to the `Platform compatibility policy`_ for the policy regarding 37compatibility and deprecation of these porting interfaces. 38 39Only Arm development platforms (such as FVP and Juno) may use the 40functions/definitions in ``include/plat/arm/common/`` and the corresponding 41source files in ``plat/arm/common/``. This is done so that there are no 42dependencies between platforms maintained by different people/companies. If you 43want to use any of the functionality present in ``plat/arm`` files, please 44create a pull request that moves the code to ``plat/common`` so that it can be 45discussed. 46 47Common modifications 48-------------------- 49 50This section covers the modifications that should be made by the platform for 51each BL stage to correctly port the firmware stack. They are categorized as 52either mandatory or optional. 53 54Common mandatory modifications 55------------------------------ 56 57A platform port must enable the Memory Management Unit (MMU) as well as the 58instruction and data caches for each BL stage. Setting up the translation 59tables is the responsibility of the platform port because memory maps differ 60across platforms. A memory translation library (see ``lib/xlat_tables/``) is 61provided to help in this setup. 62 63Note that although this library supports non-identity mappings, this is intended 64only for re-mapping peripheral physical addresses and allows platforms with high 65I/O addresses to reduce their virtual address space. All other addresses 66corresponding to code and data must currently use an identity mapping. 67 68Also, the only translation granule size supported in TF-A is 4KB, as various 69parts of the code assume that is the case. It is not possible to switch to 7016 KB or 64 KB granule sizes at the moment. 71 72In Arm standard platforms, each BL stage configures the MMU in the 73platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 74an identity mapping for all addresses. 75 76If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 77block of identity mapped secure memory with Device-nGnRE attributes aligned to 78page boundary (4K) for each BL stage. All sections which allocate coherent 79memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 80section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 81possible for the firmware to place variables in it using the following C code 82directive: 83 84:: 85 86 __section("bakery_lock") 87 88Or alternatively the following assembler code directive: 89 90:: 91 92 .section bakery_lock 93 94The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 95used to allocate any data structures that are accessed both when a CPU is 96executing with its MMU and caches enabled, and when it's running with its MMU 97and caches disabled. Examples are given below. 98 99The following variables, functions and constants must be defined by the platform 100for the firmware to work correctly. 101 102File : platform_def.h [mandatory] 103~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 104 105Each platform must ensure that a header file of this name is in the system 106include path with the following constants defined. This will require updating 107the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. 108 109Platform ports may optionally use the file `include/plat/common/common_def.h`_, 110which provides typical values for some of the constants below. These values are 111likely to be suitable for all platform ports. 112 113- **#define : PLATFORM_LINKER_FORMAT** 114 115 Defines the linker format used by the platform, for example 116 ``elf64-littleaarch64``. 117 118- **#define : PLATFORM_LINKER_ARCH** 119 120 Defines the processor architecture for the linker by the platform, for 121 example ``aarch64``. 122 123- **#define : PLATFORM_STACK_SIZE** 124 125 Defines the normal stack memory available to each CPU. This constant is used 126 by `plat/common/aarch64/platform_mp_stack.S`_ and 127 `plat/common/aarch64/platform_up_stack.S`_. 128 129- **define : CACHE_WRITEBACK_GRANULE** 130 131 Defines the size in bits of the largest cache line across all the cache 132 levels in the platform. 133 134- **#define : FIRMWARE_WELCOME_STR** 135 136 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 137 function. 138 139- **#define : PLATFORM_CORE_COUNT** 140 141 Defines the total number of CPUs implemented by the platform across all 142 clusters in the system. 143 144- **#define : PLAT_NUM_PWR_DOMAINS** 145 146 Defines the total number of nodes in the power domain topology 147 tree at all the power domain levels used by the platform. 148 This macro is used by the PSCI implementation to allocate 149 data structures to represent power domain topology. 150 151- **#define : PLAT_MAX_PWR_LVL** 152 153 Defines the maximum power domain level that the power management operations 154 should apply to. More often, but not always, the power domain level 155 corresponds to affinity level. This macro allows the PSCI implementation 156 to know the highest power domain level that it should consider for power 157 management operations in the system that the platform implements. For 158 example, the Base AEM FVP implements two clusters with a configurable 159 number of CPUs and it reports the maximum power domain level as 1. 160 161- **#define : PLAT_MAX_OFF_STATE** 162 163 Defines the local power state corresponding to the deepest power down 164 possible at every power domain level in the platform. The local power 165 states for each level may be sparsely allocated between 0 and this value 166 with 0 being reserved for the RUN state. The PSCI implementation uses this 167 value to initialize the local power states of the power domain nodes and 168 to specify the requested power state for a PSCI_CPU_OFF call. 169 170- **#define : PLAT_MAX_RET_STATE** 171 172 Defines the local power state corresponding to the deepest retention state 173 possible at every power domain level in the platform. This macro should be 174 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the 175 PSCI implementation to distinguish between retention and power down local 176 power states within PSCI_CPU_SUSPEND call. 177 178- **#define : PLAT_MAX_PWR_LVL_STATES** 179 180 Defines the maximum number of local power states per power domain level 181 that the platform supports. The default value of this macro is 2 since 182 most platforms just support a maximum of two local power states at each 183 power domain level (power-down and retention). If the platform needs to 184 account for more local power states, then it must redefine this macro. 185 186 Currently, this macro is used by the Generic PSCI implementation to size 187 the array used for PSCI_STAT_COUNT/RESIDENCY accounting. 188 189- **#define : BL1_RO_BASE** 190 191 Defines the base address in secure ROM where BL1 originally lives. Must be 192 aligned on a page-size boundary. 193 194- **#define : BL1_RO_LIMIT** 195 196 Defines the maximum address in secure ROM that BL1's actual content (i.e. 197 excluding any data section allocated at runtime) can occupy. 198 199- **#define : BL1_RW_BASE** 200 201 Defines the base address in secure RAM where BL1's read-write data will live 202 at runtime. Must be aligned on a page-size boundary. 203 204- **#define : BL1_RW_LIMIT** 205 206 Defines the maximum address in secure RAM that BL1's read-write data can 207 occupy at runtime. 208 209- **#define : BL2_BASE** 210 211 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 212 Must be aligned on a page-size boundary. This constant is not applicable 213 when BL2_IN_XIP_MEM is set to '1'. 214 215- **#define : BL2_LIMIT** 216 217 Defines the maximum address in secure RAM that the BL2 image can occupy. 218 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 219 220- **#define : BL2_RO_BASE** 221 222 Defines the base address in secure XIP memory where BL2 RO section originally 223 lives. Must be aligned on a page-size boundary. This constant is only needed 224 when BL2_IN_XIP_MEM is set to '1'. 225 226- **#define : BL2_RO_LIMIT** 227 228 Defines the maximum address in secure XIP memory that BL2's actual content 229 (i.e. excluding any data section allocated at runtime) can occupy. This 230 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 231 232- **#define : BL2_RW_BASE** 233 234 Defines the base address in secure RAM where BL2's read-write data will live 235 at runtime. Must be aligned on a page-size boundary. This constant is only 236 needed when BL2_IN_XIP_MEM is set to '1'. 237 238- **#define : BL2_RW_LIMIT** 239 240 Defines the maximum address in secure RAM that BL2's read-write data can 241 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 242 to '1'. 243 244- **#define : BL31_BASE** 245 246 Defines the base address in secure RAM where BL2 loads the BL31 binary 247 image. Must be aligned on a page-size boundary. 248 249- **#define : BL31_LIMIT** 250 251 Defines the maximum address in secure RAM that the BL31 image can occupy. 252 253For every image, the platform must define individual identifiers that will be 254used by BL1 or BL2 to load the corresponding image into memory from non-volatile 255storage. For the sake of performance, integer numbers will be used as 256identifiers. The platform will use those identifiers to return the relevant 257information about the image to be loaded (file handler, load address, 258authentication information, etc.). The following image identifiers are 259mandatory: 260 261- **#define : BL2_IMAGE_ID** 262 263 BL2 image identifier, used by BL1 to load BL2. 264 265- **#define : BL31_IMAGE_ID** 266 267 BL31 image identifier, used by BL2 to load BL31. 268 269- **#define : BL33_IMAGE_ID** 270 271 BL33 image identifier, used by BL2 to load BL33. 272 273If Trusted Board Boot is enabled, the following certificate identifiers must 274also be defined: 275 276- **#define : TRUSTED_BOOT_FW_CERT_ID** 277 278 BL2 content certificate identifier, used by BL1 to load the BL2 content 279 certificate. 280 281- **#define : TRUSTED_KEY_CERT_ID** 282 283 Trusted key certificate identifier, used by BL2 to load the trusted key 284 certificate. 285 286- **#define : SOC_FW_KEY_CERT_ID** 287 288 BL31 key certificate identifier, used by BL2 to load the BL31 key 289 certificate. 290 291- **#define : SOC_FW_CONTENT_CERT_ID** 292 293 BL31 content certificate identifier, used by BL2 to load the BL31 content 294 certificate. 295 296- **#define : NON_TRUSTED_FW_KEY_CERT_ID** 297 298 BL33 key certificate identifier, used by BL2 to load the BL33 key 299 certificate. 300 301- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** 302 303 BL33 content certificate identifier, used by BL2 to load the BL33 content 304 certificate. 305 306- **#define : FWU_CERT_ID** 307 308 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the 309 FWU content certificate. 310 311- **#define : PLAT_CRYPTOCELL_BASE** 312 313 This defines the base address of Arm® TrustZone® CryptoCell and must be 314 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 315 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 316 set. 317 318If the AP Firmware Updater Configuration image, BL2U is used, the following 319must also be defined: 320 321- **#define : BL2U_BASE** 322 323 Defines the base address in secure memory where BL1 copies the BL2U binary 324 image. Must be aligned on a page-size boundary. 325 326- **#define : BL2U_LIMIT** 327 328 Defines the maximum address in secure memory that the BL2U image can occupy. 329 330- **#define : BL2U_IMAGE_ID** 331 332 BL2U image identifier, used by BL1 to fetch an image descriptor 333 corresponding to BL2U. 334 335If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following 336must also be defined: 337 338- **#define : SCP_BL2U_IMAGE_ID** 339 340 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor 341 corresponding to SCP_BL2U. 342 NOTE: TF-A does not provide source code for this image. 343 344If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must 345also be defined: 346 347- **#define : NS_BL1U_BASE** 348 349 Defines the base address in non-secure ROM where NS_BL1U executes. 350 Must be aligned on a page-size boundary. 351 NOTE: TF-A does not provide source code for this image. 352 353- **#define : NS_BL1U_IMAGE_ID** 354 355 NS_BL1U image identifier, used by BL1 to fetch an image descriptor 356 corresponding to NS_BL1U. 357 358If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also 359be defined: 360 361- **#define : NS_BL2U_BASE** 362 363 Defines the base address in non-secure memory where NS_BL2U executes. 364 Must be aligned on a page-size boundary. 365 NOTE: TF-A does not provide source code for this image. 366 367- **#define : NS_BL2U_IMAGE_ID** 368 369 NS_BL2U image identifier, used by BL1 to fetch an image descriptor 370 corresponding to NS_BL2U. 371 372For the the Firmware update capability of TRUSTED BOARD BOOT, the following 373macros may also be defined: 374 375- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** 376 377 Total number of images that can be loaded simultaneously. If the platform 378 doesn't specify any value, it defaults to 10. 379 380If a SCP_BL2 image is supported by the platform, the following constants must 381also be defined: 382 383- **#define : SCP_BL2_IMAGE_ID** 384 385 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory 386 from platform storage before being transferred to the SCP. 387 388- **#define : SCP_FW_KEY_CERT_ID** 389 390 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key 391 certificate (mandatory when Trusted Board Boot is enabled). 392 393- **#define : SCP_FW_CONTENT_CERT_ID** 394 395 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 396 content certificate (mandatory when Trusted Board Boot is enabled). 397 398If a BL32 image is supported by the platform, the following constants must 399also be defined: 400 401- **#define : BL32_IMAGE_ID** 402 403 BL32 image identifier, used by BL2 to load BL32. 404 405- **#define : TRUSTED_OS_FW_KEY_CERT_ID** 406 407 BL32 key certificate identifier, used by BL2 to load the BL32 key 408 certificate (mandatory when Trusted Board Boot is enabled). 409 410- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** 411 412 BL32 content certificate identifier, used by BL2 to load the BL32 content 413 certificate (mandatory when Trusted Board Boot is enabled). 414 415- **#define : BL32_BASE** 416 417 Defines the base address in secure memory where BL2 loads the BL32 binary 418 image. Must be aligned on a page-size boundary. 419 420- **#define : BL32_LIMIT** 421 422 Defines the maximum address that the BL32 image can occupy. 423 424If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 425platform, the following constants must also be defined: 426 427- **#define : TSP_SEC_MEM_BASE** 428 429 Defines the base address of the secure memory used by the TSP image on the 430 platform. This must be at the same address or below ``BL32_BASE``. 431 432- **#define : TSP_SEC_MEM_SIZE** 433 434 Defines the size of the secure memory used by the BL32 image on the 435 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully 436 accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` 437 and ``BL32_LIMIT``. 438 439- **#define : TSP_IRQ_SEC_PHY_TIMER** 440 441 Defines the ID of the secure physical generic timer interrupt used by the 442 TSP's interrupt handling code. 443 444If the platform port uses the translation table library code, the following 445constants must also be defined: 446 447- **#define : PLAT_XLAT_TABLES_DYNAMIC** 448 449 Optional flag that can be set per-image to enable the dynamic allocation of 450 regions even when the MMU is enabled. If not defined, only static 451 functionality will be available, if defined and set to 1 it will also 452 include the dynamic functionality. 453 454- **#define : MAX_XLAT_TABLES** 455 456 Defines the maximum number of translation tables that are allocated by the 457 translation table library code. To minimize the amount of runtime memory 458 used, choose the smallest value needed to map the required virtual addresses 459 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 460 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 461 as well. 462 463- **#define : MAX_MMAP_REGIONS** 464 465 Defines the maximum number of regions that are allocated by the translation 466 table library code. A region consists of physical base address, virtual base 467 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 468 defined in the ``mmap_region_t`` structure. The platform defines the regions 469 that should be mapped. Then, the translation table library will create the 470 corresponding tables and descriptors at runtime. To minimize the amount of 471 runtime memory used, choose the smallest value needed to register the 472 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 473 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 474 the dynamic regions as well. 475 476- **#define : PLAT_VIRT_ADDR_SPACE_SIZE** 477 478 Defines the total size of the virtual address space in bytes. For example, 479 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 480 481- **#define : PLAT_PHY_ADDR_SPACE_SIZE** 482 483 Defines the total size of the physical address space in bytes. For example, 484 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 485 486If the platform port uses the IO storage framework, the following constants 487must also be defined: 488 489- **#define : MAX_IO_DEVICES** 490 491 Defines the maximum number of registered IO devices. Attempting to register 492 more devices than this value using ``io_register_device()`` will fail with 493 -ENOMEM. 494 495- **#define : MAX_IO_HANDLES** 496 497 Defines the maximum number of open IO handles. Attempting to open more IO 498 entities than this value using ``io_open()`` will fail with -ENOMEM. 499 500- **#define : MAX_IO_BLOCK_DEVICES** 501 502 Defines the maximum number of registered IO block devices. Attempting to 503 register more devices this value using ``io_dev_open()`` will fail 504 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. 505 With this macro, multiple block devices could be supported at the same 506 time. 507 508If the platform needs to allocate data within the per-cpu data framework in 509BL31, it should define the following macro. Currently this is only required if 510the platform decides not to use the coherent memory section by undefining the 511``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 512required memory within the the per-cpu data to minimize wastage. 513 514- **#define : PLAT_PCPU_DATA_SIZE** 515 516 Defines the memory (in bytes) to be reserved within the per-cpu data 517 structure for use by the platform layer. 518 519The following constants are optional. They should be defined when the platform 520memory layout implies some image overlaying like in Arm standard platforms. 521 522- **#define : BL31_PROGBITS_LIMIT** 523 524 Defines the maximum address in secure RAM that the BL31's progbits sections 525 can occupy. 526 527- **#define : TSP_PROGBITS_LIMIT** 528 529 Defines the maximum address that the TSP's progbits sections can occupy. 530 531If the platform port uses the PL061 GPIO driver, the following constant may 532optionally be defined: 533 534- **PLAT_PL061_MAX_GPIOS** 535 Maximum number of GPIOs required by the platform. This allows control how 536 much memory is allocated for PL061 GPIO controllers. The default value is 537 538 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) 539 540If the platform port uses the partition driver, the following constant may 541optionally be defined: 542 543- **PLAT_PARTITION_MAX_ENTRIES** 544 Maximum number of partition entries required by the platform. This allows 545 control how much memory is allocated for partition entries. The default 546 value is 128. 547 `For example, define the build flag in platform.mk`_: 548 PLAT_PARTITION_MAX_ENTRIES := 12 549 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) 550 551The following constant is optional. It should be defined to override the default 552behaviour of the ``assert()`` function (for example, to save memory). 553 554- **PLAT_LOG_LEVEL_ASSERT** 555 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 556 ``assert()`` prints the name of the file, the line number and the asserted 557 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 558 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 559 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 560 defined, it defaults to ``LOG_LEVEL``. 561 562If the platform port uses the Activity Monitor Unit, the following constants 563may be defined: 564 565- **PLAT_AMU_GROUP1_COUNTERS_MASK** 566 This mask reflects the set of group counters that should be enabled. The 567 maximum number of group 1 counters supported by AMUv1 is 16 so the mask 568 can be at most 0xffff. If the platform does not define this mask, no group 1 569 counters are enabled. If the platform defines this mask, the following 570 constant needs to also be defined. 571 572- **PLAT_AMU_GROUP1_NR_COUNTERS** 573 This value is used to allocate an array to save and restore the counters 574 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend. 575 This value should be equal to the highest bit position set in the 576 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16. 577 578File : plat_macros.S [mandatory] 579~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 580 581Each platform must ensure a file of this name is in the system include path with 582the following macro defined. In the Arm development platforms, this file is 583found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 584 585- **Macro : plat_crash_print_regs** 586 587 This macro allows the crash reporting routine to print relevant platform 588 registers in case of an unhandled exception in BL31. This aids in debugging 589 and this macro can be defined to be empty in case register reporting is not 590 desired. 591 592 For instance, GIC or interconnect registers may be helpful for 593 troubleshooting. 594 595Handling Reset 596-------------- 597 598BL1 by default implements the reset vector where execution starts from a cold 599or warm boot. BL31 can be optionally set as a reset vector using the 600``RESET_TO_BL31`` make variable. 601 602For each CPU, the reset vector code is responsible for the following tasks: 603 604#. Distinguishing between a cold boot and a warm boot. 605 606#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 607 the CPU is placed in a platform-specific state until the primary CPU 608 performs the necessary steps to remove it from this state. 609 610#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 611 specific address in the BL31 image in the same processor mode as it was 612 when released from reset. 613 614The following functions need to be implemented by the platform port to enable 615reset vector code to perform the above tasks. 616 617Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] 618~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 619 620:: 621 622 Argument : void 623 Return : uintptr_t 624 625This function is called with the MMU and caches disabled 626(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 627distinguishing between a warm and cold reset for the current CPU using 628platform-specific means. If it's a warm reset, then it returns the warm 629reset entrypoint point provided to ``plat_setup_psci_ops()`` during 630BL31 initialization. If it's a cold reset then this function must return zero. 631 632This function does not follow the Procedure Call Standard used by the 633Application Binary Interface for the Arm 64-bit architecture. The caller should 634not assume that callee saved registers are preserved across a call to this 635function. 636 637This function fulfills requirement 1 and 3 listed above. 638 639Note that for platforms that support programming the reset address, it is 640expected that a CPU will start executing code directly at the right address, 641both on a cold and warm reset. In this case, there is no need to identify the 642type of reset nor to query the warm reset entrypoint. Therefore, implementing 643this function is not required on such platforms. 644 645Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 646~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 647 648:: 649 650 Argument : void 651 652This function is called with the MMU and data caches disabled. It is responsible 653for placing the executing secondary CPU in a platform-specific state until the 654primary CPU performs the necessary actions to bring it out of that state and 655allow entry into the OS. This function must not return. 656 657In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 658itself off. The primary CPU is responsible for powering up the secondary CPUs 659when normal world software requires them. When booting an EL3 payload instead, 660they stay powered on and are put in a holding pen until their mailbox gets 661populated. 662 663This function fulfills requirement 2 above. 664 665Note that for platforms that can't release secondary CPUs out of reset, only the 666primary CPU will execute the cold boot code. Therefore, implementing this 667function is not required on such platforms. 668 669Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 670~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 671 672:: 673 674 Argument : void 675 Return : unsigned int 676 677This function identifies whether the current CPU is the primary CPU or a 678secondary CPU. A return value of zero indicates that the CPU is not the 679primary CPU, while a non-zero return value indicates that the CPU is the 680primary CPU. 681 682Note that for platforms that can't release secondary CPUs out of reset, only the 683primary CPU will execute the cold boot code. Therefore, there is no need to 684distinguish between primary and secondary CPUs and implementing this function is 685not required. 686 687Function : platform_mem_init() [mandatory] 688~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 689 690:: 691 692 Argument : void 693 Return : void 694 695This function is called before any access to data is made by the firmware, in 696order to carry out any essential memory initialization. 697 698Function: plat_get_rotpk_info() 699~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 700 701:: 702 703 Argument : void *, void **, unsigned int *, unsigned int * 704 Return : int 705 706This function is mandatory when Trusted Board Boot is enabled. It returns a 707pointer to the ROTPK stored in the platform (or a hash of it) and its length. 708The ROTPK must be encoded in DER format according to the following ASN.1 709structure: 710 711:: 712 713 AlgorithmIdentifier ::= SEQUENCE { 714 algorithm OBJECT IDENTIFIER, 715 parameters ANY DEFINED BY algorithm OPTIONAL 716 } 717 718 SubjectPublicKeyInfo ::= SEQUENCE { 719 algorithm AlgorithmIdentifier, 720 subjectPublicKey BIT STRING 721 } 722 723In case the function returns a hash of the key: 724 725:: 726 727 DigestInfo ::= SEQUENCE { 728 digestAlgorithm AlgorithmIdentifier, 729 digest OCTET STRING 730 } 731 732The function returns 0 on success. Any other value is treated as error by the 733Trusted Board Boot. The function also reports extra information related 734to the ROTPK in the flags parameter: 735 736:: 737 738 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 739 hash. 740 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 741 verification while the platform ROTPK is not deployed. 742 When this flag is set, the function does not need to 743 return a platform ROTPK, and the authentication 744 framework uses the ROTPK in the certificate without 745 verifying it against the platform value. This flag 746 must not be used in a deployed production environment. 747 748Function: plat_get_nv_ctr() 749~~~~~~~~~~~~~~~~~~~~~~~~~~~ 750 751:: 752 753 Argument : void *, unsigned int * 754 Return : int 755 756This function is mandatory when Trusted Board Boot is enabled. It returns the 757non-volatile counter value stored in the platform in the second argument. The 758cookie in the first argument may be used to select the counter in case the 759platform provides more than one (for example, on platforms that use the default 760TBBR CoT, the cookie will correspond to the OID values defined in 761TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). 762 763The function returns 0 on success. Any other value means the counter value could 764not be retrieved from the platform. 765 766Function: plat_set_nv_ctr() 767~~~~~~~~~~~~~~~~~~~~~~~~~~~ 768 769:: 770 771 Argument : void *, unsigned int 772 Return : int 773 774This function is mandatory when Trusted Board Boot is enabled. It sets a new 775counter value in the platform. The cookie in the first argument may be used to 776select the counter (as explained in plat_get_nv_ctr()). The second argument is 777the updated counter value to be written to the NV counter. 778 779The function returns 0 on success. Any other value means the counter value could 780not be updated. 781 782Function: plat_set_nv_ctr2() 783~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 784 785:: 786 787 Argument : void *, const auth_img_desc_t *, unsigned int 788 Return : int 789 790This function is optional when Trusted Board Boot is enabled. If this 791interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 792first argument passed is a cookie and is typically used to 793differentiate between a Non Trusted NV Counter and a Trusted NV 794Counter. The second argument is a pointer to an authentication image 795descriptor and may be used to decide if the counter is allowed to be 796updated or not. The third argument is the updated counter value to 797be written to the NV counter. 798 799The function returns 0 on success. Any other value means the counter value 800either could not be updated or the authentication image descriptor indicates 801that it is not allowed to be updated. 802 803Common mandatory function modifications 804--------------------------------------- 805 806The following functions are mandatory functions which need to be implemented 807by the platform port. 808 809Function : plat_my_core_pos() 810~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 811 812:: 813 814 Argument : void 815 Return : unsigned int 816 817This function returns the index of the calling CPU which is used as a 818CPU-specific linear index into blocks of memory (for example while allocating 819per-CPU stacks). This function will be invoked very early in the 820initialization sequence which mandates that this function should be 821implemented in assembly and should not rely on the availability of a C 822runtime environment. This function can clobber x0 - x8 and must preserve 823x9 - x29. 824 825This function plays a crucial role in the power domain topology framework in 826PSCI and details of this can be found in `Power Domain Topology Design`_. 827 828Function : plat_core_pos_by_mpidr() 829~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 830 831:: 832 833 Argument : u_register_t 834 Return : int 835 836This function validates the ``MPIDR`` of a CPU and converts it to an index, 837which can be used as a CPU-specific linear index into blocks of memory. In 838case the ``MPIDR`` is invalid, this function returns -1. This function will only 839be invoked by BL31 after the power domain topology is initialized and can 840utilize the C runtime environment. For further details about how TF-A 841represents the power domain topology and how this relates to the linear CPU 842index, please refer `Power Domain Topology Design`_. 843 844Common optional modifications 845----------------------------- 846 847The following are helper functions implemented by the firmware that perform 848common platform-specific tasks. A platform may choose to override these 849definitions. 850 851Function : plat_set_my_stack() 852~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 853 854:: 855 856 Argument : void 857 Return : void 858 859This function sets the current stack pointer to the normal memory stack that 860has been allocated for the current CPU. For BL images that only require a 861stack for the primary CPU, the UP version of the function is used. The size 862of the stack allocated to each CPU is specified by the platform defined 863constant ``PLATFORM_STACK_SIZE``. 864 865Common implementations of this function for the UP and MP BL images are 866provided in `plat/common/aarch64/platform_up_stack.S`_ and 867`plat/common/aarch64/platform_mp_stack.S`_ 868 869Function : plat_get_my_stack() 870~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 871 872:: 873 874 Argument : void 875 Return : uintptr_t 876 877This function returns the base address of the normal memory stack that 878has been allocated for the current CPU. For BL images that only require a 879stack for the primary CPU, the UP version of the function is used. The size 880of the stack allocated to each CPU is specified by the platform defined 881constant ``PLATFORM_STACK_SIZE``. 882 883Common implementations of this function for the UP and MP BL images are 884provided in `plat/common/aarch64/platform_up_stack.S`_ and 885`plat/common/aarch64/platform_mp_stack.S`_ 886 887Function : plat_report_exception() 888~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 889 890:: 891 892 Argument : unsigned int 893 Return : void 894 895A platform may need to report various information about its status when an 896exception is taken, for example the current exception level, the CPU security 897state (secure/non-secure), the exception type, and so on. This function is 898called in the following circumstances: 899 900- In BL1, whenever an exception is taken. 901- In BL2, whenever an exception is taken. 902 903The default implementation doesn't do anything, to avoid making assumptions 904about the way the platform displays its status information. 905 906For AArch64, this function receives the exception type as its argument. 907Possible values for exceptions types are listed in the 908`include/common/bl_common.h`_ header file. Note that these constants are not 909related to any architectural exception code; they are just a TF-A convention. 910 911For AArch32, this function receives the exception mode as its argument. 912Possible values for exception modes are listed in the 913`include/lib/aarch32/arch.h`_ header file. 914 915Function : plat_reset_handler() 916~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 917 918:: 919 920 Argument : void 921 Return : void 922 923A platform may need to do additional initialization after reset. This function 924allows the platform to do the platform specific intializations. Platform 925specific errata workarounds could also be implemented here. The API should 926preserve the values of callee saved registers x19 to x29. 927 928The default implementation doesn't do anything. If a platform needs to override 929the default implementation, refer to the `Firmware Design`_ for general 930guidelines. 931 932Function : plat_disable_acp() 933~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 934 935:: 936 937 Argument : void 938 Return : void 939 940This API allows a platform to disable the Accelerator Coherency Port (if 941present) during a cluster power down sequence. The default weak implementation 942doesn't do anything. Since this API is called during the power down sequence, 943it has restrictions for stack usage and it can use the registers x0 - x17 as 944scratch registers. It should preserve the value in x18 register as it is used 945by the caller to store the return address. 946 947Function : plat_error_handler() 948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 949 950:: 951 952 Argument : int 953 Return : void 954 955This API is called when the generic code encounters an error situation from 956which it cannot continue. It allows the platform to perform error reporting or 957recovery actions (for example, reset the system). This function must not return. 958 959The parameter indicates the type of error using standard codes from ``errno.h``. 960Possible errors reported by the generic code are: 961 962- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 963 Board Boot is enabled) 964- ``-ENOENT``: the requested image or certificate could not be found or an IO 965 error was detected 966- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 967 error is usually an indication of an incorrect array size 968 969The default implementation simply spins. 970 971Function : plat_panic_handler() 972~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 973 974:: 975 976 Argument : void 977 Return : void 978 979This API is called when the generic code encounters an unexpected error 980situation from which it cannot recover. This function must not return, 981and must be implemented in assembly because it may be called before the C 982environment is initialized. 983 984Note: The address from where it was called is stored in x30 (Link Register). 985The default implementation simply spins. 986 987Function : plat_get_bl_image_load_info() 988~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 989 990:: 991 992 Argument : void 993 Return : bl_load_info_t * 994 995This function returns pointer to the list of images that the platform has 996populated to load. This function is invoked in BL2 to load the 997BL3xx images. 998 999Function : plat_get_next_bl_params() 1000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1001 1002:: 1003 1004 Argument : void 1005 Return : bl_params_t * 1006 1007This function returns a pointer to the shared memory that the platform has 1008kept aside to pass TF-A related information that next BL image needs. This 1009function is invoked in BL2 to pass this information to the next BL 1010image. 1011 1012Function : plat_get_stack_protector_canary() 1013~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1014 1015:: 1016 1017 Argument : void 1018 Return : u_register_t 1019 1020This function returns a random value that is used to initialize the canary used 1021when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable 1022value will weaken the protection as the attacker could easily write the right 1023value as part of the attack most of the time. Therefore, it should return a 1024true random number. 1025 1026Note: For the protection to be effective, the global data need to be placed at 1027a lower address than the stack bases. Failure to do so would allow an attacker 1028to overwrite the canary as part of the stack buffer overflow attack. 1029 1030Function : plat_flush_next_bl_params() 1031~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1032 1033:: 1034 1035 Argument : void 1036 Return : void 1037 1038This function flushes to main memory all the image params that are passed to 1039next image. This function is invoked in BL2 to flush this information 1040to the next BL image. 1041 1042Function : plat_log_get_prefix() 1043~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1044 1045:: 1046 1047 Argument : unsigned int 1048 Return : const char * 1049 1050This function defines the prefix string corresponding to the `log_level` to be 1051prepended to all the log output from TF-A. The `log_level` (argument) will 1052correspond to one of the standard log levels defined in debug.h. The platform 1053can override the common implementation to define a different prefix string for 1054the log output. The implementation should be robust to future changes that 1055increase the number of log levels. 1056 1057Function : plat_get_mbedtls_heap() 1058~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1059 1060:: 1061 1062 Arguments : void **heap_addr, size_t *heap_size 1063 Return : int 1064 1065This function is invoked during Mbed TLS library initialisation to get 1066a heap, by means of a starting address and a size. This heap will then be used 1067internally by the Mbed TLS library. The heap is requested from the current BL 1068stage, i.e. the current BL image inside which Mbed TLS is used. 1069 1070In the default implementation a heap is statically allocated inside every image 1071(i.e. every BL stage) that utilises Mbed TLS. So, in this case, the function 1072simply returns the address and size of this "pre-allocated" heap. However, by 1073overriding the default implementation, platforms have the potential to optimise 1074memory usage. For example, on some Arm platforms, the Mbed TLS heap is shared 1075between BL1 and BL2 stages and, thus, the necessary space is not reserved 1076twice. 1077 1078On success the function should return 0 and a negative error code otherwise. 1079 1080Modifications specific to a Boot Loader stage 1081--------------------------------------------- 1082 1083Boot Loader Stage 1 (BL1) 1084------------------------- 1085 1086BL1 implements the reset vector where execution starts from after a cold or 1087warm boot. For each CPU, BL1 is responsible for the following tasks: 1088 1089#. Handling the reset as described in section 2.2 1090 1091#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1092 only this CPU executes the remaining BL1 code, including loading and passing 1093 control to the BL2 stage. 1094 1095#. Identifying and starting the Firmware Update process (if required). 1096 1097#. Loading the BL2 image from non-volatile storage into secure memory at the 1098 address specified by the platform defined constant ``BL2_BASE``. 1099 1100#. Populating a ``meminfo`` structure with the following information in memory, 1101 accessible by BL2 immediately upon entry. 1102 1103 :: 1104 1105 meminfo.total_base = Base address of secure RAM visible to BL2 1106 meminfo.total_size = Size of secure RAM visible to BL2 1107 1108 By default, BL1 places this ``meminfo`` structure at the end of secure 1109 memory visible to BL2. 1110 1111 It is possible for the platform to decide where it wants to place the 1112 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1113 BL2 by overriding the weak default implementation of 1114 ``bl1_plat_handle_post_image_load`` API. 1115 1116The following functions need to be implemented by the platform port to enable 1117BL1 to perform the above tasks. 1118 1119Function : bl1_early_platform_setup() [mandatory] 1120~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1121 1122:: 1123 1124 Argument : void 1125 Return : void 1126 1127This function executes with the MMU and data caches disabled. It is only called 1128by the primary CPU. 1129 1130On Arm standard platforms, this function: 1131 1132- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1133 1134- Initializes a UART (PL011 console), which enables access to the ``printf`` 1135 family of functions in BL1. 1136 1137- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1138 the CCI slave interface corresponding to the cluster that includes the 1139 primary CPU. 1140 1141Function : bl1_plat_arch_setup() [mandatory] 1142~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1143 1144:: 1145 1146 Argument : void 1147 Return : void 1148 1149This function performs any platform-specific and architectural setup that the 1150platform requires. Platform-specific setup might include configuration of 1151memory controllers and the interconnect. 1152 1153In Arm standard platforms, this function enables the MMU. 1154 1155This function helps fulfill requirement 2 above. 1156 1157Function : bl1_platform_setup() [mandatory] 1158~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1159 1160:: 1161 1162 Argument : void 1163 Return : void 1164 1165This function executes with the MMU and data caches enabled. It is responsible 1166for performing any remaining platform-specific setup that can occur after the 1167MMU and data cache have been enabled. 1168 1169if support for multiple boot sources is required, it initializes the boot 1170sequence used by plat_try_next_boot_source(). 1171 1172In Arm standard platforms, this function initializes the storage abstraction 1173layer used to load the next bootloader image. 1174 1175This function helps fulfill requirement 4 above. 1176 1177Function : bl1_plat_sec_mem_layout() [mandatory] 1178~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1179 1180:: 1181 1182 Argument : void 1183 Return : meminfo * 1184 1185This function should only be called on the cold boot path. It executes with the 1186MMU and data caches enabled. The pointer returned by this function must point to 1187a ``meminfo`` structure containing the extents and availability of secure RAM for 1188the BL1 stage. 1189 1190:: 1191 1192 meminfo.total_base = Base address of secure RAM visible to BL1 1193 meminfo.total_size = Size of secure RAM visible to BL1 1194 1195This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1196populates a similar structure to tell BL2 the extents of memory available for 1197its own use. 1198 1199This function helps fulfill requirements 4 and 5 above. 1200 1201Function : bl1_plat_prepare_exit() [optional] 1202~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1203 1204:: 1205 1206 Argument : entry_point_info_t * 1207 Return : void 1208 1209This function is called prior to exiting BL1 in response to the 1210``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1211platform specific clean up or bookkeeping operations before transferring 1212control to the next image. It receives the address of the ``entry_point_info_t`` 1213structure passed from BL2. This function runs with MMU disabled. 1214 1215Function : bl1_plat_set_ep_info() [optional] 1216~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1217 1218:: 1219 1220 Argument : unsigned int image_id, entry_point_info_t *ep_info 1221 Return : void 1222 1223This function allows platforms to override ``ep_info`` for the given ``image_id``. 1224 1225The default implementation just returns. 1226 1227Function : bl1_plat_get_next_image_id() [optional] 1228~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1229 1230:: 1231 1232 Argument : void 1233 Return : unsigned int 1234 1235This and the following function must be overridden to enable the FWU feature. 1236 1237BL1 calls this function after platform setup to identify the next image to be 1238loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1239with the normal boot sequence, which loads and executes BL2. If the platform 1240returns a different image id, BL1 assumes that Firmware Update is required. 1241 1242The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1243platforms override this function to detect if firmware update is required, and 1244if so, return the first image in the firmware update process. 1245 1246Function : bl1_plat_get_image_desc() [optional] 1247~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1248 1249:: 1250 1251 Argument : unsigned int image_id 1252 Return : image_desc_t * 1253 1254BL1 calls this function to get the image descriptor information ``image_desc_t`` 1255for the provided ``image_id`` from the platform. 1256 1257The default implementation always returns a common BL2 image descriptor. Arm 1258standard platforms return an image descriptor corresponding to BL2 or one of 1259the firmware update images defined in the Trusted Board Boot Requirements 1260specification. 1261 1262Function : bl1_plat_handle_pre_image_load() [optional] 1263~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1264 1265:: 1266 1267 Argument : unsigned int image_id 1268 Return : int 1269 1270This function can be used by the platforms to update/use image information 1271corresponding to ``image_id``. This function is invoked in BL1, both in cold 1272boot and FWU code path, before loading the image. 1273 1274Function : bl1_plat_handle_post_image_load() [optional] 1275~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1276 1277:: 1278 1279 Argument : unsigned int image_id 1280 Return : int 1281 1282This function can be used by the platforms to update/use image information 1283corresponding to ``image_id``. This function is invoked in BL1, both in cold 1284boot and FWU code path, after loading and authenticating the image. 1285 1286The default weak implementation of this function calculates the amount of 1287Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1288structure at the beginning of this free memory and populates it. The address 1289of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1290information to BL2. 1291 1292Function : bl1_plat_fwu_done() [optional] 1293~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1294 1295:: 1296 1297 Argument : unsigned int image_id, uintptr_t image_src, 1298 unsigned int image_size 1299 Return : void 1300 1301BL1 calls this function when the FWU process is complete. It must not return. 1302The platform may override this function to take platform specific action, for 1303example to initiate the normal boot flow. 1304 1305The default implementation spins forever. 1306 1307Function : bl1_plat_mem_check() [mandatory] 1308~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1309 1310:: 1311 1312 Argument : uintptr_t mem_base, unsigned int mem_size, 1313 unsigned int flags 1314 Return : int 1315 1316BL1 calls this function while handling FWU related SMCs, more specifically when 1317copying or authenticating an image. Its responsibility is to ensure that the 1318region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1319that this memory corresponds to either a secure or non-secure memory region as 1320indicated by the security state of the ``flags`` argument. 1321 1322This function can safely assume that the value resulting from the addition of 1323``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1324overflow. 1325 1326This function must return 0 on success, a non-null error code otherwise. 1327 1328The default implementation of this function asserts therefore platforms must 1329override it when using the FWU feature. 1330 1331Boot Loader Stage 2 (BL2) 1332------------------------- 1333 1334The BL2 stage is executed only by the primary CPU, which is determined in BL1 1335using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1336``BL2_BASE``. BL2 executes in Secure EL1 and and invokes 1337``plat_get_bl_image_load_info()`` to retrieve the list of images to load from 1338non-volatile storage to secure/non-secure RAM. After all the images are loaded 1339then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable 1340images to be passed to the next BL image. 1341 1342The following functions must be implemented by the platform port to enable BL2 1343to perform the above tasks. 1344 1345Function : bl2_early_platform_setup2() [mandatory] 1346~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1347 1348:: 1349 1350 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1351 Return : void 1352 1353This function executes with the MMU and data caches disabled. It is only called 1354by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments 1355are platform specific. 1356 1357On Arm standard platforms, the arguments received are : 1358 1359 arg0 - Points to load address of HW_CONFIG if present 1360 1361 arg1 - ``meminfo`` structure populated by BL1. The platform copies 1362 the contents of ``meminfo`` as it may be subsequently overwritten by BL2. 1363 1364On Arm standard platforms, this function also: 1365 1366- Initializes a UART (PL011 console), which enables access to the ``printf`` 1367 family of functions in BL2. 1368 1369- Initializes the storage abstraction layer used to load further bootloader 1370 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1371 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1372 1373Function : bl2_plat_arch_setup() [mandatory] 1374~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1375 1376:: 1377 1378 Argument : void 1379 Return : void 1380 1381This function executes with the MMU and data caches disabled. It is only called 1382by the primary CPU. 1383 1384The purpose of this function is to perform any architectural initialization 1385that varies across platforms. 1386 1387On Arm standard platforms, this function enables the MMU. 1388 1389Function : bl2_platform_setup() [mandatory] 1390~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1391 1392:: 1393 1394 Argument : void 1395 Return : void 1396 1397This function may execute with the MMU and data caches enabled if the platform 1398port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1399called by the primary CPU. 1400 1401The purpose of this function is to perform any platform initialization 1402specific to BL2. 1403 1404In Arm standard platforms, this function performs security setup, including 1405configuration of the TrustZone controller to allow non-secure masters access 1406to most of DRAM. Part of DRAM is reserved for secure world use. 1407 1408Function : bl2_plat_handle_pre_image_load() [optional] 1409~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1410 1411:: 1412 1413 Argument : unsigned int 1414 Return : int 1415 1416This function can be used by the platforms to update/use image information 1417for given ``image_id``. This function is currently invoked in BL2 before 1418loading each image. 1419 1420Function : bl2_plat_handle_post_image_load() [optional] 1421~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1422 1423:: 1424 1425 Argument : unsigned int 1426 Return : int 1427 1428This function can be used by the platforms to update/use image information 1429for given ``image_id``. This function is currently invoked in BL2 after 1430loading each image. 1431 1432Function : bl2_plat_preload_setup [optional] 1433~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1434 1435:: 1436 1437 Argument : void 1438 Return : void 1439 1440This optional function performs any BL2 platform initialization 1441required before image loading, that is not done later in 1442bl2_platform_setup(). Specifically, if support for multiple 1443boot sources is required, it initializes the boot sequence used by 1444plat_try_next_boot_source(). 1445 1446Function : plat_try_next_boot_source() [optional] 1447~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1448 1449:: 1450 1451 Argument : void 1452 Return : int 1453 1454This optional function passes to the next boot source in the redundancy 1455sequence. 1456 1457This function moves the current boot redundancy source to the next 1458element in the boot sequence. If there are no more boot sources then it 1459must return 0, otherwise it must return 1. The default implementation 1460of this always returns 0. 1461 1462Boot Loader Stage 2 (BL2) at EL3 1463-------------------------------- 1464 1465When the platform has a non-TF-A Boot ROM it is desirable to jump 1466directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1467execute at EL3 instead of executing at EL1. Refer to the `Firmware 1468Design`_ for more information. 1469 1470All mandatory functions of BL2 must be implemented, except the functions 1471bl2_early_platform_setup and bl2_el3_plat_arch_setup, because 1472their work is done now by bl2_el3_early_platform_setup and 1473bl2_el3_plat_arch_setup. These functions should generally implement 1474the bl1_plat_xxx() and bl2_plat_xxx() functionality combined. 1475 1476 1477Function : bl2_el3_early_platform_setup() [mandatory] 1478~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1479 1480:: 1481 1482 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1483 Return : void 1484 1485This function executes with the MMU and data caches disabled. It is only called 1486by the primary CPU. This function receives four parameters which can be used 1487by the platform to pass any needed information from the Boot ROM to BL2. 1488 1489On Arm standard platforms, this function does the following: 1490 1491- Initializes a UART (PL011 console), which enables access to the ``printf`` 1492 family of functions in BL2. 1493 1494- Initializes the storage abstraction layer used to load further bootloader 1495 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1496 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1497 1498- Initializes the private variables that define the memory layout used. 1499 1500Function : bl2_el3_plat_arch_setup() [mandatory] 1501~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1502 1503:: 1504 1505 Argument : void 1506 Return : void 1507 1508This function executes with the MMU and data caches disabled. It is only called 1509by the primary CPU. 1510 1511The purpose of this function is to perform any architectural initialization 1512that varies across platforms. 1513 1514On Arm standard platforms, this function enables the MMU. 1515 1516Function : bl2_el3_plat_prepare_exit() [optional] 1517~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1518 1519:: 1520 1521 Argument : void 1522 Return : void 1523 1524This function is called prior to exiting BL2 and run the next image. 1525It should be used to perform platform specific clean up or bookkeeping 1526operations before transferring control to the next image. This function 1527runs with MMU disabled. 1528 1529FWU Boot Loader Stage 2 (BL2U) 1530------------------------------ 1531 1532The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1533process and is executed only by the primary CPU. BL1 passes control to BL2U at 1534``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1535 1536#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure 1537 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. 1538 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U 1539 should be copied from. Subsequent handling of the SCP_BL2U image is 1540 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1541 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1542 1543#. Any platform specific setup required to perform the FWU process. For 1544 example, Arm standard platforms initialize the TZC controller so that the 1545 normal world can access DDR memory. 1546 1547The following functions must be implemented by the platform port to enable 1548BL2U to perform the tasks mentioned above. 1549 1550Function : bl2u_early_platform_setup() [mandatory] 1551~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1552 1553:: 1554 1555 Argument : meminfo *mem_info, void *plat_info 1556 Return : void 1557 1558This function executes with the MMU and data caches disabled. It is only 1559called by the primary CPU. The arguments to this function is the address 1560of the ``meminfo`` structure and platform specific info provided by BL1. 1561 1562The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1563private storage as the original memory may be subsequently overwritten by BL2U. 1564 1565On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1566to extract SCP_BL2U image information, which is then copied into a private 1567variable. 1568 1569Function : bl2u_plat_arch_setup() [mandatory] 1570~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1571 1572:: 1573 1574 Argument : void 1575 Return : void 1576 1577This function executes with the MMU and data caches disabled. It is only 1578called by the primary CPU. 1579 1580The purpose of this function is to perform any architectural initialization 1581that varies across platforms, for example enabling the MMU (since the memory 1582map differs across platforms). 1583 1584Function : bl2u_platform_setup() [mandatory] 1585~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1586 1587:: 1588 1589 Argument : void 1590 Return : void 1591 1592This function may execute with the MMU and data caches enabled if the platform 1593port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1594called by the primary CPU. 1595 1596The purpose of this function is to perform any platform initialization 1597specific to BL2U. 1598 1599In Arm standard platforms, this function performs security setup, including 1600configuration of the TrustZone controller to allow non-secure masters access 1601to most of DRAM. Part of DRAM is reserved for secure world use. 1602 1603Function : bl2u_plat_handle_scp_bl2u() [optional] 1604~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1605 1606:: 1607 1608 Argument : void 1609 Return : int 1610 1611This function is used to perform any platform-specific actions required to 1612handle the SCP firmware. Typically it transfers the image into SCP memory using 1613a platform-specific protocol and waits until SCP executes it and signals to the 1614Application Processor (AP) for BL2U execution to continue. 1615 1616This function returns 0 on success, a negative error code otherwise. 1617This function is included if SCP_BL2U_BASE is defined. 1618 1619Boot Loader Stage 3-1 (BL31) 1620---------------------------- 1621 1622During cold boot, the BL31 stage is executed only by the primary CPU. This is 1623determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1624control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1625CPUs. BL31 executes at EL3 and is responsible for: 1626 1627#. Re-initializing all architectural and platform state. Although BL1 performs 1628 some of this initialization, BL31 remains resident in EL3 and must ensure 1629 that EL3 architectural and platform state is completely initialized. It 1630 should make no assumptions about the system state when it receives control. 1631 1632#. Passing control to a normal world BL image, pre-loaded at a platform- 1633 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list 1634 populated by BL2 in memory to do this. 1635 1636#. Providing runtime firmware services. Currently, BL31 only implements a 1637 subset of the Power State Coordination Interface (PSCI) API as a runtime 1638 service. See Section 3.3 below for details of porting the PSCI 1639 implementation. 1640 1641#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1642 specific address by BL2. BL31 exports a set of APIs that allow runtime 1643 services to specify the security state in which the next image should be 1644 executed and run the corresponding image. On ARM platforms, BL31 uses the 1645 ``bl_params`` list populated by BL2 in memory to do this. 1646 1647If BL31 is a reset vector, It also needs to handle the reset as specified in 1648section 2.2 before the tasks described above. 1649 1650The following functions must be implemented by the platform port to enable BL31 1651to perform the above tasks. 1652 1653Function : bl31_early_platform_setup2() [mandatory] 1654~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1655 1656:: 1657 1658 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1659 Return : void 1660 1661This function executes with the MMU and data caches disabled. It is only called 1662by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are 1663platform specific. 1664 1665In Arm standard platforms, the arguments received are : 1666 1667 arg0 - The pointer to the head of `bl_params_t` list 1668 which is list of executable images following BL31, 1669 1670 arg1 - Points to load address of SOC_FW_CONFIG if present 1671 1672 arg2 - Points to load address of HW_CONFIG if present 1673 1674 arg3 - A special value to verify platform parameters from BL2 to BL31. Not 1675 used in release builds. 1676 1677The function runs through the `bl_param_t` list and extracts the entry point 1678information for BL32 and BL33. It also performs the following: 1679 1680- Initialize a UART (PL011 console), which enables access to the ``printf`` 1681 family of functions in BL31. 1682 1683- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1684 CCI slave interface corresponding to the cluster that includes the primary 1685 CPU. 1686 1687Function : bl31_plat_arch_setup() [mandatory] 1688~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1689 1690:: 1691 1692 Argument : void 1693 Return : void 1694 1695This function executes with the MMU and data caches disabled. It is only called 1696by the primary CPU. 1697 1698The purpose of this function is to perform any architectural initialization 1699that varies across platforms. 1700 1701On Arm standard platforms, this function enables the MMU. 1702 1703Function : bl31_platform_setup() [mandatory] 1704~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1705 1706:: 1707 1708 Argument : void 1709 Return : void 1710 1711This function may execute with the MMU and data caches enabled if the platform 1712port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1713called by the primary CPU. 1714 1715The purpose of this function is to complete platform initialization so that both 1716BL31 runtime services and normal world software can function correctly. 1717 1718On Arm standard platforms, this function does the following: 1719 1720- Initialize the generic interrupt controller. 1721 1722 Depending on the GIC driver selected by the platform, the appropriate GICv2 1723 or GICv3 initialization will be done, which mainly consists of: 1724 1725 - Enable secure interrupts in the GIC CPU interface. 1726 - Disable the legacy interrupt bypass mechanism. 1727 - Configure the priority mask register to allow interrupts of all priorities 1728 to be signaled to the CPU interface. 1729 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1730 - Target all secure SPIs to CPU0. 1731 - Enable these secure interrupts in the GIC distributor. 1732 - Configure all other interrupts as non-secure. 1733 - Enable signaling of secure interrupts in the GIC distributor. 1734 1735- Enable system-level implementation of the generic timer counter through the 1736 memory mapped interface. 1737 1738- Grant access to the system counter timer module 1739 1740- Initialize the power controller device. 1741 1742 In particular, initialise the locks that prevent concurrent accesses to the 1743 power controller device. 1744 1745Function : bl31_plat_runtime_setup() [optional] 1746~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1747 1748:: 1749 1750 Argument : void 1751 Return : void 1752 1753The purpose of this function is allow the platform to perform any BL31 runtime 1754setup just prior to BL31 exit during cold boot. The default weak 1755implementation of this function will invoke ``console_switch_state()`` to switch 1756console output to consoles marked for use in the ``runtime`` state. 1757 1758Function : bl31_plat_get_next_image_ep_info() [mandatory] 1759~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1760 1761:: 1762 1763 Argument : uint32_t 1764 Return : entry_point_info * 1765 1766This function may execute with the MMU and data caches enabled if the platform 1767port does the necessary initializations in ``bl31_plat_arch_setup()``. 1768 1769This function is called by ``bl31_main()`` to retrieve information provided by 1770BL2 for the next image in the security state specified by the argument. BL31 1771uses this information to pass control to that image in the specified security 1772state. This function must return a pointer to the ``entry_point_info`` structure 1773(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 1774should return NULL otherwise. 1775 1776Function : bl31_plat_enable_mmu [optional] 1777~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1778 1779:: 1780 1781 Argument : uint32_t 1782 Return : void 1783 1784This function enables the MMU. The boot code calls this function with MMU and 1785caches disabled. This function should program necessary registers to enable 1786translation, and upon return, the MMU on the calling PE must be enabled. 1787 1788The function must honor flags passed in the first argument. These flags are 1789defined by the translation library, and can be found in the file 1790``include/lib/xlat_tables/xlat_mmu_helpers.h``. 1791 1792On DynamIQ systems, this function must not use stack while enabling MMU, which 1793is how the function in xlat table library version 2 is implemented. 1794 1795Function : plat_init_apiakey [optional] 1796~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1797 1798:: 1799 1800 Argument : void 1801 Return : uint64_t * 1802 1803This function populates the ``plat_apiakey`` array that contains the values used 1804to set the ``APIAKey{Hi,Lo}_EL1`` registers. It returns a pointer to this array. 1805 1806The value should be obtained from a reliable source of randomness. 1807 1808This function is only needed if ARMv8.3 pointer authentication is used in the 1809Trusted Firmware by building with ``ENABLE_PAUTH=1``. 1810 1811Function : plat_get_syscnt_freq2() [mandatory] 1812~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1813 1814:: 1815 1816 Argument : void 1817 Return : unsigned int 1818 1819This function is used by the architecture setup code to retrieve the counter 1820frequency for the CPU's generic timer. This value will be programmed into the 1821``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 1822of the system counter, which is retrieved from the first entry in the frequency 1823modes table. 1824 1825#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] 1826~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1827 1828When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 1829bytes) aligned to the cache line boundary that should be allocated per-cpu to 1830accommodate all the bakery locks. 1831 1832If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 1833calculates the size of the ``bakery_lock`` input section, aligns it to the 1834nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 1835and stores the result in a linker symbol. This constant prevents a platform 1836from relying on the linker and provide a more efficient mechanism for 1837accessing per-cpu bakery lock information. 1838 1839If this constant is defined and its value is not equal to the value 1840calculated by the linker then a link time assertion is raised. A compile time 1841assertion is raised if the value of the constant is not aligned to the cache 1842line boundary. 1843 1844SDEI porting requirements 1845~~~~~~~~~~~~~~~~~~~~~~~~~ 1846 1847The SDEI dispatcher requires the platform to provide the following macros 1848and functions, of which some are optional, and some others mandatory. 1849 1850Macros 1851...... 1852 1853Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 1854^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1855 1856This macro must be defined to the EL3 exception priority level associated with 1857Normal SDEI events on the platform. This must have a higher value (therefore of 1858lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 1859 1860Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 1861^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1862 1863This macro must be defined to the EL3 exception priority level associated with 1864Critical SDEI events on the platform. This must have a lower value (therefore of 1865higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 1866 1867**Note**: SDEI exception priorities must be the lowest among Secure priorities. 1868Among the SDEI exceptions, Critical SDEI priority must be higher than Normal 1869SDEI priority. 1870 1871Functions 1872......... 1873 1874Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional] 1875^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1876 1877:: 1878 1879 Argument: uintptr_t 1880 Return: int 1881 1882This function validates the address of client entry points provided for both 1883event registration and *Complete and Resume* SDEI calls. The function takes one 1884argument, which is the address of the handler the SDEI client requested to 1885register. The function must return ``0`` for successful validation, or ``-1`` 1886upon failure. 1887 1888The default implementation always returns ``0``. On Arm platforms, this function 1889is implemented to translate the entry point to physical address, and further to 1890ensure that the address is located in Non-secure DRAM. 1891 1892Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 1893^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1894 1895:: 1896 1897 Argument: uint64_t 1898 Argument: unsigned int 1899 Return: void 1900 1901SDEI specification requires that a PE comes out of reset with the events masked. 1902The client therefore is expected to call ``PE_UNMASK`` to unmask SDEI events on 1903the PE. No SDEI events can be dispatched until such time. 1904 1905Should a PE receive an interrupt that was bound to an SDEI event while the 1906events are masked on the PE, the dispatcher implementation invokes the function 1907``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 1908interrupt and the interrupt ID are passed as parameters. 1909 1910The default implementation only prints out a warning message. 1911 1912Power State Coordination Interface (in BL31) 1913-------------------------------------------- 1914 1915The TF-A implementation of the PSCI API is based around the concept of a 1916*power domain*. A *power domain* is a CPU or a logical group of CPUs which 1917share some state on which power management operations can be performed as 1918specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 1919a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 1920*power domains* are arranged in a hierarchical tree structure and each 1921*power domain* can be identified in a system by the cpu index of any CPU that 1922is part of that domain and a *power domain level*. A processing element (for 1923example, a CPU) is at level 0. If the *power domain* node above a CPU is a 1924logical grouping of CPUs that share some state, then level 1 is that group of 1925CPUs (for example, a cluster), and level 2 is a group of clusters (for 1926example, the system). More details on the power domain topology and its 1927organization can be found in `Power Domain Topology Design`_. 1928 1929BL31's platform initialization code exports a pointer to the platform-specific 1930power management operations required for the PSCI implementation to function 1931correctly. This information is populated in the ``plat_psci_ops`` structure. The 1932PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 1933power management operations on the power domains. For example, the target 1934CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 1935handler (if present) is called for the CPU power domain. 1936 1937The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 1938describe composite power states specific to a platform. The PSCI implementation 1939defines a generic representation of the power-state parameter, which is an 1940array of local power states where each index corresponds to a power domain 1941level. Each entry contains the local power state the power domain at that power 1942level could enter. It depends on the ``validate_power_state()`` handler to 1943convert the power-state parameter (possibly encoding a composite power state) 1944passed in a PSCI ``CPU_SUSPEND`` call to this representation. 1945 1946The following functions form part of platform port of PSCI functionality. 1947 1948Function : plat_psci_stat_accounting_start() [optional] 1949~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1950 1951:: 1952 1953 Argument : const psci_power_state_t * 1954 Return : void 1955 1956This is an optional hook that platforms can implement for residency statistics 1957accounting before entering a low power state. The ``pwr_domain_state`` field of 1958``state_info`` (first argument) can be inspected if stat accounting is done 1959differently at CPU level versus higher levels. As an example, if the element at 1960index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 1961state, special hardware logic may be programmed in order to keep track of the 1962residency statistics. For higher levels (array indices > 0), the residency 1963statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 1964default implementation will use PMF to capture timestamps. 1965 1966Function : plat_psci_stat_accounting_stop() [optional] 1967~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1968 1969:: 1970 1971 Argument : const psci_power_state_t * 1972 Return : void 1973 1974This is an optional hook that platforms can implement for residency statistics 1975accounting after exiting from a low power state. The ``pwr_domain_state`` field 1976of ``state_info`` (first argument) can be inspected if stat accounting is done 1977differently at CPU level versus higher levels. As an example, if the element at 1978index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 1979state, special hardware logic may be programmed in order to keep track of the 1980residency statistics. For higher levels (array indices > 0), the residency 1981statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 1982default implementation will use PMF to capture timestamps. 1983 1984Function : plat_psci_stat_get_residency() [optional] 1985~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1986 1987:: 1988 1989 Argument : unsigned int, const psci_power_state_t *, int 1990 Return : u_register_t 1991 1992This is an optional interface that is is invoked after resuming from a low power 1993state and provides the time spent resident in that low power state by the power 1994domain at a particular power domain level. When a CPU wakes up from suspend, 1995all its parent power domain levels are also woken up. The generic PSCI code 1996invokes this function for each parent power domain that is resumed and it 1997identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 1998argument) describes the low power state that the power domain has resumed from. 1999The current CPU is the first CPU in the power domain to resume from the low 2000power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2001CPU in the power domain to suspend and may be needed to calculate the residency 2002for that power domain. 2003 2004Function : plat_get_target_pwr_state() [optional] 2005~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2006 2007:: 2008 2009 Argument : unsigned int, const plat_local_state_t *, unsigned int 2010 Return : plat_local_state_t 2011 2012The PSCI generic code uses this function to let the platform participate in 2013state coordination during a power management operation. The function is passed 2014a pointer to an array of platform specific local power state ``states`` (second 2015argument) which contains the requested power state for each CPU at a particular 2016power domain level ``lvl`` (first argument) within the power domain. The function 2017is expected to traverse this array of upto ``ncpus`` (third argument) and return 2018a coordinated target power state by the comparing all the requested power 2019states. The target power state should not be deeper than any of the requested 2020power states. 2021 2022A weak definition of this API is provided by default wherein it assumes 2023that the platform assigns a local state value in order of increasing depth 2024of the power state i.e. for two power states X & Y, if X < Y 2025then X represents a shallower power state than Y. As a result, the 2026coordinated target local power state for a power domain will be the minimum 2027of the requested local power state values. 2028 2029Function : plat_get_power_domain_tree_desc() [mandatory] 2030~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2031 2032:: 2033 2034 Argument : void 2035 Return : const unsigned char * 2036 2037This function returns a pointer to the byte array containing the power domain 2038topology tree description. The format and method to construct this array are 2039described in `Power Domain Topology Design`_. The BL31 PSCI initialization code 2040requires this array to be described by the platform, either statically or 2041dynamically, to initialize the power domain topology tree. In case the array 2042is populated dynamically, then plat_core_pos_by_mpidr() and 2043plat_my_core_pos() should also be implemented suitably so that the topology 2044tree description matches the CPU indices returned by these APIs. These APIs 2045together form the platform interface for the PSCI topology framework. 2046 2047Function : plat_setup_psci_ops() [mandatory] 2048~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2049 2050:: 2051 2052 Argument : uintptr_t, const plat_psci_ops ** 2053 Return : int 2054 2055This function may execute with the MMU and data caches enabled if the platform 2056port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2057called by the primary CPU. 2058 2059This function is called by PSCI initialization code. Its purpose is to let 2060the platform layer know about the warm boot entrypoint through the 2061``sec_entrypoint`` (first argument) and to export handler routines for 2062platform-specific psci power management actions by populating the passed 2063pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2064 2065A description of each member of this structure is given below. Please refer to 2066the Arm FVP specific implementation of these handlers in 2067`plat/arm/board/fvp/fvp_pm.c`_ as an example. For each PSCI function that the 2068platform wants to support, the associated operation or operations in this 2069structure must be provided and implemented (Refer section 4 of 2070`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI 2071function in a platform port, the operation should be removed from this 2072structure instead of providing an empty implementation. 2073 2074plat_psci_ops.cpu_standby() 2075........................... 2076 2077Perform the platform-specific actions to enter the standby state for a cpu 2078indicated by the passed argument. This provides a fast path for CPU standby 2079wherein overheads of PSCI state management and lock acquisition is avoided. 2080For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2081the suspend state type specified in the ``power-state`` parameter should be 2082STANDBY and the target power domain level specified should be the CPU. The 2083handler should put the CPU into a low power retention state (usually by 2084issuing a wfi instruction) and ensure that it can be woken up from that 2085state by a normal interrupt. The generic code expects the handler to succeed. 2086 2087plat_psci_ops.pwr_domain_on() 2088............................. 2089 2090Perform the platform specific actions to power on a CPU, specified 2091by the ``MPIDR`` (first argument). The generic code expects the platform to 2092return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. 2093 2094plat_psci_ops.pwr_domain_off() 2095.............................. 2096 2097Perform the platform specific actions to prepare to power off the calling CPU 2098and its higher parent power domain levels as indicated by the ``target_state`` 2099(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2100 2101The ``target_state`` encodes the platform coordinated target local power states 2102for the CPU power domain and its parent power domain levels. The handler 2103needs to perform power management operation corresponding to the local state 2104at each power level. 2105 2106For this handler, the local power state for the CPU power domain will be a 2107power down state where as it could be either power down, retention or run state 2108for the higher power domain levels depending on the result of state 2109coordination. The generic code expects the handler to succeed. 2110 2111plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] 2112........................................................... 2113 2114This optional function may be used as a performance optimization to replace 2115or complement pwr_domain_suspend() on some platforms. Its calling semantics 2116are identical to pwr_domain_suspend(), except the PSCI implementation only 2117calls this function when suspending to a power down state, and it guarantees 2118that data caches are enabled. 2119 2120When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2121before calling pwr_domain_suspend(). If the target_state corresponds to a 2122power down state and it is safe to perform some or all of the platform 2123specific actions in that function with data caches enabled, it may be more 2124efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2125= 1, data caches remain enabled throughout, and so there is no advantage to 2126moving platform specific actions to this function. 2127 2128plat_psci_ops.pwr_domain_suspend() 2129.................................. 2130 2131Perform the platform specific actions to prepare to suspend the calling 2132CPU and its higher parent power domain levels as indicated by the 2133``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2134API implementation. 2135 2136The ``target_state`` has a similar meaning as described in 2137the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2138target local power states for the CPU power domain and its parent 2139power domain levels. The handler needs to perform power management operation 2140corresponding to the local state at each power level. The generic code 2141expects the handler to succeed. 2142 2143The difference between turning a power domain off versus suspending it is that 2144in the former case, the power domain is expected to re-initialize its state 2145when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2146case, the power domain is expected to save enough state so that it can resume 2147execution by restoring this state when its powered on (see 2148``pwr_domain_suspend_finish()``). 2149 2150When suspending a core, the platform can also choose to power off the GICv3 2151Redistributor and ITS through an implementation-defined sequence. To achieve 2152this safely, the ITS context must be saved first. The architectural part is 2153implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2154sequence is implementation defined and it is therefore the responsibility of 2155the platform code to implement the necessary sequence. Then the GIC 2156Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2157Powering off the Redistributor requires the implementation to support it and it 2158is the responsibility of the platform code to execute the right implementation 2159defined sequence. 2160 2161When a system suspend is requested, the platform can also make use of the 2162``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2163it has saved the context of the Redistributors and ITS of all the cores in the 2164system. The context of the Distributor can be large and may require it to be 2165allocated in a special area if it cannot fit in the platform's global static 2166data, for example in DRAM. The Distributor can then be powered down using an 2167implementation-defined sequence. 2168 2169plat_psci_ops.pwr_domain_pwr_down_wfi() 2170....................................... 2171 2172This is an optional function and, if implemented, is expected to perform 2173platform specific actions including the ``wfi`` invocation which allows the 2174CPU to powerdown. Since this function is invoked outside the PSCI locks, 2175the actions performed in this hook must be local to the CPU or the platform 2176must ensure that races between multiple CPUs cannot occur. 2177 2178The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2179operation and it encodes the platform coordinated target local power states for 2180the CPU power domain and its parent power domain levels. This function must 2181not return back to the caller. 2182 2183If this function is not implemented by the platform, PSCI generic 2184implementation invokes ``psci_power_down_wfi()`` for power down. 2185 2186plat_psci_ops.pwr_domain_on_finish() 2187.................................... 2188 2189This function is called by the PSCI implementation after the calling CPU is 2190powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2191It performs the platform-specific setup required to initialize enough state for 2192this CPU to enter the normal world and also provide secure runtime firmware 2193services. 2194 2195The ``target_state`` (first argument) is the prior state of the power domains 2196immediately before the CPU was turned on. It indicates which power domains 2197above the CPU might require initialization due to having previously been in 2198low power states. The generic code expects the handler to succeed. 2199 2200plat_psci_ops.pwr_domain_suspend_finish() 2201......................................... 2202 2203This function is called by the PSCI implementation after the calling CPU is 2204powered on and released from reset in response to an asynchronous wakeup 2205event, for example a timer interrupt that was programmed by the CPU during the 2206``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2207setup required to restore the saved state for this CPU to resume execution 2208in the normal world and also provide secure runtime firmware services. 2209 2210The ``target_state`` (first argument) has a similar meaning as described in 2211the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2212to succeed. 2213 2214If the Distributor, Redistributors or ITS have been powered off as part of a 2215suspend, their context must be restored in this function in the reverse order 2216to how they were saved during suspend sequence. 2217 2218plat_psci_ops.system_off() 2219.......................... 2220 2221This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2222call. It performs the platform-specific system poweroff sequence after 2223notifying the Secure Payload Dispatcher. 2224 2225plat_psci_ops.system_reset() 2226............................ 2227 2228This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2229call. It performs the platform-specific system reset sequence after 2230notifying the Secure Payload Dispatcher. 2231 2232plat_psci_ops.validate_power_state() 2233.................................... 2234 2235This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2236call to validate the ``power_state`` parameter of the PSCI API and if valid, 2237populate it in ``req_state`` (second argument) array as power domain level 2238specific local states. If the ``power_state`` is invalid, the platform must 2239return PSCI_E_INVALID_PARAMS as error, which is propagated back to the 2240normal world PSCI client. 2241 2242plat_psci_ops.validate_ns_entrypoint() 2243...................................... 2244 2245This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2246``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2247parameter passed by the normal world. If the ``entry_point`` is invalid, 2248the platform must return PSCI_E_INVALID_ADDRESS as error, which is 2249propagated back to the normal world PSCI client. 2250 2251plat_psci_ops.get_sys_suspend_power_state() 2252........................................... 2253 2254This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2255call to get the ``req_state`` parameter from platform which encodes the power 2256domain level specific local states to suspend to system affinity level. The 2257``req_state`` will be utilized to do the PSCI state coordination and 2258``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2259enter system suspend. 2260 2261plat_psci_ops.get_pwr_lvl_state_idx() 2262..................................... 2263 2264This is an optional function and, if implemented, is invoked by the PSCI 2265implementation to convert the ``local_state`` (first argument) at a specified 2266``pwr_lvl`` (second argument) to an index between 0 and 2267``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2268supports more than two local power states at each power domain level, that is 2269``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2270local power states. 2271 2272plat_psci_ops.translate_power_state_by_mpidr() 2273.............................................. 2274 2275This is an optional function and, if implemented, verifies the ``power_state`` 2276(second argument) parameter of the PSCI API corresponding to a target power 2277domain. The target power domain is identified by using both ``MPIDR`` (first 2278argument) and the power domain level encoded in ``power_state``. The power domain 2279level specific local states are to be extracted from ``power_state`` and be 2280populated in the ``output_state`` (third argument) array. The functionality 2281is similar to the ``validate_power_state`` function described above and is 2282envisaged to be used in case the validity of ``power_state`` depend on the 2283targeted power domain. If the ``power_state`` is invalid for the targeted power 2284domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this 2285function is not implemented, then the generic implementation relies on 2286``validate_power_state`` function to translate the ``power_state``. 2287 2288This function can also be used in case the platform wants to support local 2289power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY 2290APIs as described in Section 5.18 of `PSCI`_. 2291 2292plat_psci_ops.get_node_hw_state() 2293................................. 2294 2295This is an optional function. If implemented this function is intended to return 2296the power state of a node (identified by the first parameter, the ``MPIDR``) in 2297the power domain topology (identified by the second parameter, ``power_level``), 2298as retrieved from a power controller or equivalent component on the platform. 2299Upon successful completion, the implementation must map and return the final 2300status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2301must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2302appropriate. 2303 2304Implementations are not expected to handle ``power_levels`` greater than 2305``PLAT_MAX_PWR_LVL``. 2306 2307plat_psci_ops.system_reset2() 2308............................. 2309 2310This is an optional function. If implemented this function is 2311called during the ``SYSTEM_RESET2`` call to perform a reset 2312based on the first parameter ``reset_type`` as specified in 2313`PSCI`_. The parameter ``cookie`` can be used to pass additional 2314reset information. If the ``reset_type`` is not supported, the 2315function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2316resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2317and vendor reset can return other PSCI error codes as defined 2318in `PSCI`_. On success this function will not return. 2319 2320plat_psci_ops.write_mem_protect() 2321................................. 2322 2323This is an optional function. If implemented it enables or disables the 2324``MEM_PROTECT`` functionality based on the value of ``val``. 2325A non-zero value enables ``MEM_PROTECT`` and a value of zero 2326disables it. Upon encountering failures it must return a negative value 2327and on success it must return 0. 2328 2329plat_psci_ops.read_mem_protect() 2330................................ 2331 2332This is an optional function. If implemented it returns the current 2333state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2334failures it must return a negative value and on success it must 2335return 0. 2336 2337plat_psci_ops.mem_protect_chk() 2338............................... 2339 2340This is an optional function. If implemented it checks if a memory 2341region defined by a base address ``base`` and with a size of ``length`` 2342bytes is protected by ``MEM_PROTECT``. If the region is protected 2343then it must return 0, otherwise it must return a negative number. 2344 2345Interrupt Management framework (in BL31) 2346---------------------------------------- 2347 2348BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2349generated in either security state and targeted to EL1 or EL2 in the non-secure 2350state or EL3/S-EL1 in the secure state. The design of this framework is 2351described in the `IMF Design Guide`_ 2352 2353A platform should export the following APIs to support the IMF. The following 2354text briefly describes each API and its implementation in Arm standard 2355platforms. The API implementation depends upon the type of interrupt controller 2356present in the platform. Arm standard platform layer supports both 2357`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 2358and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 2359FVP can be configured to use either GICv2 or GICv3 depending on the build flag 2360``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in 2361`User Guide`_ for more details). 2362 2363See also: `Interrupt Controller Abstraction APIs`__. 2364 2365.. __: platform-interrupt-controller-API.rst 2366 2367Function : plat_interrupt_type_to_line() [mandatory] 2368~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2369 2370:: 2371 2372 Argument : uint32_t, uint32_t 2373 Return : uint32_t 2374 2375The Arm processor signals an interrupt exception either through the IRQ or FIQ 2376interrupt line. The specific line that is signaled depends on how the interrupt 2377controller (IC) reports different interrupt types from an execution context in 2378either security state. The IMF uses this API to determine which interrupt line 2379the platform IC uses to signal each type of interrupt supported by the framework 2380from a given security state. This API must be invoked at EL3. 2381 2382The first parameter will be one of the ``INTR_TYPE_*`` values (see 2383`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the 2384security state of the originating execution context. The return result is the 2385bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1, 2386FIQ=2. 2387 2388In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 2389configured as FIQs and Non-secure interrupts as IRQs from either security 2390state. 2391 2392In the case of Arm standard platforms using GICv3, the interrupt line to be 2393configured depends on the security state of the execution context when the 2394interrupt is signalled and are as follows: 2395 2396- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2397 NS-EL0/1/2 context. 2398- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2399 in the NS-EL0/1/2 context. 2400- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2401 context. 2402 2403Function : plat_ic_get_pending_interrupt_type() [mandatory] 2404~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2405 2406:: 2407 2408 Argument : void 2409 Return : uint32_t 2410 2411This API returns the type of the highest priority pending interrupt at the 2412platform IC. The IMF uses the interrupt type to retrieve the corresponding 2413handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2414pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2415``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2416 2417In the case of Arm standard platforms using GICv2, the *Highest Priority 2418Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2419the pending interrupt. The type of interrupt depends upon the id value as 2420follows. 2421 2422#. id < 1022 is reported as a S-EL1 interrupt 2423#. id = 1022 is reported as a Non-secure interrupt. 2424#. id = 1023 is reported as an invalid interrupt type. 2425 2426In the case of Arm standard platforms using GICv3, the system register 2427``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2428is read to determine the id of the pending interrupt. The type of interrupt 2429depends upon the id value as follows. 2430 2431#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2432#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2433#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2434#. All other interrupt id's are reported as EL3 interrupt. 2435 2436Function : plat_ic_get_pending_interrupt_id() [mandatory] 2437~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2438 2439:: 2440 2441 Argument : void 2442 Return : uint32_t 2443 2444This API returns the id of the highest priority pending interrupt at the 2445platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2446pending. 2447 2448In the case of Arm standard platforms using GICv2, the *Highest Priority 2449Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2450pending interrupt. The id that is returned by API depends upon the value of 2451the id read from the interrupt controller as follows. 2452 2453#. id < 1022. id is returned as is. 2454#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2455 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2456 This id is returned by the API. 2457#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2458 2459In the case of Arm standard platforms using GICv3, if the API is invoked from 2460EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2461group 0 Register*, is read to determine the id of the pending interrupt. The id 2462that is returned by API depends upon the value of the id read from the 2463interrupt controller as follows. 2464 2465#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2466#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2467 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2468 Register* is read to determine the id of the group 1 interrupt. This id 2469 is returned by the API as long as it is a valid interrupt id 2470#. If the id is any of the special interrupt identifiers, 2471 ``INTR_ID_UNAVAILABLE`` is returned. 2472 2473When the API invoked from S-EL1 for GICv3 systems, the id read from system 2474register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2475Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else 2476``INTR_ID_UNAVAILABLE`` is returned. 2477 2478Function : plat_ic_acknowledge_interrupt() [mandatory] 2479~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2480 2481:: 2482 2483 Argument : void 2484 Return : uint32_t 2485 2486This API is used by the CPU to indicate to the platform IC that processing of 2487the highest pending interrupt has begun. It should return the raw, unmodified 2488value obtained from the interrupt controller when acknowledging an interrupt. 2489The actual interrupt number shall be extracted from this raw value using the API 2490`plat_ic_get_interrupt_id()`__. 2491 2492.. __: platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional 2493 2494This function in Arm standard platforms using GICv2, reads the *Interrupt 2495Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2496priority pending interrupt from pending to active in the interrupt controller. 2497It returns the value read from the ``GICC_IAR``, unmodified. 2498 2499In the case of Arm standard platforms using GICv3, if the API is invoked 2500from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2501Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2502reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2503group 1*. The read changes the state of the highest pending interrupt from 2504pending to active in the interrupt controller. The value read is returned 2505unmodified. 2506 2507The TSP uses this API to start processing of the secure physical timer 2508interrupt. 2509 2510Function : plat_ic_end_of_interrupt() [mandatory] 2511~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2512 2513:: 2514 2515 Argument : uint32_t 2516 Return : void 2517 2518This API is used by the CPU to indicate to the platform IC that processing of 2519the interrupt corresponding to the id (passed as the parameter) has 2520finished. The id should be the same as the id returned by the 2521``plat_ic_acknowledge_interrupt()`` API. 2522 2523Arm standard platforms write the id to the *End of Interrupt Register* 2524(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2525system register in case of GICv3 depending on where the API is invoked from, 2526EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2527controller. 2528 2529The TSP uses this API to finish processing of the secure physical timer 2530interrupt. 2531 2532Function : plat_ic_get_interrupt_type() [mandatory] 2533~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2534 2535:: 2536 2537 Argument : uint32_t 2538 Return : uint32_t 2539 2540This API returns the type of the interrupt id passed as the parameter. 2541``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2542interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2543returned depending upon how the interrupt has been configured by the platform 2544IC. This API must be invoked at EL3. 2545 2546Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2547and Non-secure interrupts as Group1 interrupts. It reads the group value 2548corresponding to the interrupt id from the relevant *Interrupt Group Register* 2549(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2550 2551In the case of Arm standard platforms using GICv3, both the *Interrupt Group 2552Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2553(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2554as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2555 2556Crash Reporting mechanism (in BL31) 2557----------------------------------- 2558 2559BL31 implements a crash reporting mechanism which prints the various registers 2560of the CPU to enable quick crash analysis and debugging. This mechanism relies 2561on the platform implementing ``plat_crash_console_init``, 2562``plat_crash_console_putc`` and ``plat_crash_console_flush``. 2563 2564The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample 2565implementation of all of them. Platforms may include this file to their 2566makefiles in order to benefit from them. By default, they will cause the crash 2567output to be routed over the normal console infrastructure and get printed on 2568consoles configured to output in crash state. ``console_set_scope()`` can be 2569used to control whether a console is used for crash output. 2570NOTE: Platforms are responsible for making sure that they only mark consoles for 2571use in the crash scope that are able to support this, i.e. that are written in 2572assembly and conform with the register clobber rules for putc() (x0-x2, x16-x17) 2573and flush() (x0-x3, x16-x17) crash callbacks. 2574 2575In some cases (such as debugging very early crashes that happen before the 2576normal boot console can be set up), platforms may want to control crash output 2577more explicitly. These platforms may instead provide custom implementations for 2578these. They are executed outside of a C environment and without a stack. Many 2579console drivers provide functions named ``console_xxx_core_init/putc/flush`` 2580that are designed to be used by these functions. See Arm platforms (like juno) 2581for an example of this. 2582 2583Function : plat_crash_console_init [mandatory] 2584~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2585 2586:: 2587 2588 Argument : void 2589 Return : int 2590 2591This API is used by the crash reporting mechanism to initialize the crash 2592console. It must only use the general purpose registers x0 through x7 to do the 2593initialization and returns 1 on success. 2594 2595Function : plat_crash_console_putc [mandatory] 2596~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2597 2598:: 2599 2600 Argument : int 2601 Return : int 2602 2603This API is used by the crash reporting mechanism to print a character on the 2604designated crash console. It must only use general purpose registers x1 and 2605x2 to do its work. The parameter and the return value are in general purpose 2606register x0. 2607 2608Function : plat_crash_console_flush [mandatory] 2609~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2610 2611:: 2612 2613 Argument : void 2614 Return : int 2615 2616This API is used by the crash reporting mechanism to force write of all buffered 2617data on the designated crash console. It should only use general purpose 2618registers x0 through x5 to do its work. The return value is 0 on successful 2619completion; otherwise the return value is -1. 2620 2621External Abort handling and RAS Support 2622--------------------------------------- 2623 2624Function : plat_ea_handler 2625~~~~~~~~~~~~~~~~~~~~~~~~~~ 2626 2627:: 2628 2629 Argument : int 2630 Argument : uint64_t 2631 Argument : void * 2632 Argument : void * 2633 Argument : uint64_t 2634 Return : void 2635 2636This function is invoked by the RAS framework for the platform to handle an 2637External Abort received at EL3. The intention of the function is to attempt to 2638resolve the cause of External Abort and return; if that's not possible, to 2639initiate orderly shutdown of the system. 2640 2641The first parameter (``int ea_reason``) indicates the reason for External Abort. 2642Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 2643 2644The second parameter (``uint64_t syndrome``) is the respective syndrome 2645presented to EL3 after having received the External Abort. Depending on the 2646nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 2647can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 2648 2649The third parameter (``void *cookie``) is unused for now. The fourth parameter 2650(``void *handle``) is a pointer to the preempted context. The fifth parameter 2651(``uint64_t flags``) indicates the preempted security state. These parameters 2652are received from the top-level exception handler. 2653 2654If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this 2655function iterates through RAS handlers registered by the platform. If any of the 2656RAS handlers resolve the External Abort, no further action is taken. 2657 2658If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers 2659could resolve the External Abort, the default implementation prints an error 2660message, and panics. 2661 2662Function : plat_handle_uncontainable_ea 2663~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2664 2665:: 2666 2667 Argument : int 2668 Argument : uint64_t 2669 Return : void 2670 2671This function is invoked by the RAS framework when an External Abort of 2672Uncontainable type is received at EL3. Due to the critical nature of 2673Uncontainable errors, the intention of this function is to initiate orderly 2674shutdown of the system, and is not expected to return. 2675 2676This function must be implemented in assembly. 2677 2678The first and second parameters are the same as that of ``plat_ea_handler``. 2679 2680The default implementation of this function calls 2681``report_unhandled_exception``. 2682 2683Function : plat_handle_double_fault 2684~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2685 2686:: 2687 2688 Argument : int 2689 Argument : uint64_t 2690 Return : void 2691 2692This function is invoked by the RAS framework when another External Abort is 2693received at EL3 while one is already being handled. I.e., a call to 2694``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 2695this function is to initiate orderly shutdown of the system, and is not expected 2696recover or return. 2697 2698This function must be implemented in assembly. 2699 2700The first and second parameters are the same as that of ``plat_ea_handler``. 2701 2702The default implementation of this function calls 2703``report_unhandled_exception``. 2704 2705Function : plat_handle_el3_ea 2706~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2707 2708:: 2709 2710 Return : void 2711 2712This function is invoked when an External Abort is received while executing in 2713EL3. Due to its critical nature, the intention of this function is to initiate 2714orderly shutdown of the system, and is not expected recover or return. 2715 2716This function must be implemented in assembly. 2717 2718The default implementation of this function calls 2719``report_unhandled_exception``. 2720 2721Build flags 2722----------- 2723 2724There are some build flags which can be defined by the platform to control 2725inclusion or exclusion of certain BL stages from the FIP image. These flags 2726need to be defined in the platform makefile which will get included by the 2727build system. 2728 2729- **NEED_BL33** 2730 By default, this flag is defined ``yes`` by the build system and ``BL33`` 2731 build option should be supplied as a build option. The platform has the 2732 option of excluding the BL33 image in the ``fip`` image by defining this flag 2733 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 2734 are used, this flag will be set to ``no`` automatically. 2735 2736C Library 2737--------- 2738 2739To avoid subtle toolchain behavioral dependencies, the header files provided 2740by the compiler are not used. The software is built with the ``-nostdinc`` flag 2741to ensure no headers are included from the toolchain inadvertently. Instead the 2742required headers are included in the TF-A source tree. The library only 2743contains those C library definitions required by the local implementation. If 2744more functionality is required, the needed library functions will need to be 2745added to the local implementation. 2746 2747Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 2748been written specifically for TF-A. Fome implementation files have been obtained 2749from `FreeBSD`_, others have been written specifically for TF-A as well. The 2750files can be found in ``include/lib/libc`` and ``lib/libc``. 2751 2752SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources 2753can be obtained from http://github.com/freebsd/freebsd. 2754 2755Storage abstraction layer 2756------------------------- 2757 2758In order to improve platform independence and portability an storage abstraction 2759layer is used to load data from non-volatile platform storage. 2760 2761Each platform should register devices and their drivers via the Storage layer. 2762These drivers then need to be initialized by bootloader phases as 2763required in their respective ``blx_platform_setup()`` functions. Currently 2764storage access is only required by BL1 and BL2 phases. The ``load_image()`` 2765function uses the storage layer to access non-volatile platform storage. 2766 2767It is mandatory to implement at least one storage driver. For the Arm 2768development platforms the Firmware Image Package (FIP) driver is provided as 2769the default means to load data from storage (see the "Firmware Image Package" 2770section in the `User Guide`_). The storage layer is described in the header file 2771``include/drivers/io/io_storage.h``. The implementation of the common library 2772is in ``drivers/io/io_storage.c`` and the driver files are located in 2773``drivers/io/``. 2774 2775Each IO driver must provide ``io_dev_*`` structures, as described in 2776``drivers/io/io_driver.h``. These are returned via a mandatory registration 2777function that is called on platform initialization. The semi-hosting driver 2778implementation in ``io_semihosting.c`` can be used as an example. 2779 2780The Storage layer provides mechanisms to initialize storage devices before 2781IO operations are called. The basic operations supported by the layer 2782include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 2783Drivers do not have to implement all operations, but each platform must 2784provide at least one driver for a device capable of supporting generic 2785operations such as loading a bootloader image. 2786 2787The current implementation only allows for known images to be loaded by the 2788firmware. These images are specified by using their identifiers, as defined in 2789``include/plat/common/common_def.h`` (or a separate header file included from 2790there). The platform layer (``plat_get_image_source()``) then returns a reference 2791to a device and a driver-specific ``spec`` which will be understood by the driver 2792to allow access to the image data. 2793 2794The layer is designed in such a way that is it possible to chain drivers with 2795other drivers. For example, file-system drivers may be implemented on top of 2796physical block devices, both represented by IO devices with corresponding 2797drivers. In such a case, the file-system "binding" with the block device may 2798be deferred until the file-system device is initialised. 2799 2800The abstraction currently depends on structures being statically allocated 2801by the drivers and callers, as the system does not yet provide a means of 2802dynamically allocating memory. This may also have the affect of limiting the 2803amount of open resources per driver. 2804 2805-------------- 2806 2807*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* 2808 2809.. _include/plat/common/platform.h: ../include/plat/common/platform.h 2810.. _include/plat/arm/common/plat_arm.h: ../include/plat/arm/common/plat_arm.h%5D 2811.. _User Guide: user-guide.rst 2812.. _include/plat/common/common_def.h: ../include/plat/common/common_def.h 2813.. _include/plat/arm/common/arm_def.h: ../include/plat/arm/common/arm_def.h 2814.. _plat/common/aarch64/platform_mp_stack.S: ../plat/common/aarch64/platform_mp_stack.S 2815.. _plat/common/aarch64/platform_up_stack.S: ../plat/common/aarch64/platform_up_stack.S 2816.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160 2817.. _Power Domain Topology Design: psci-pd-tree.rst 2818.. _include/common/bl_common.h: ../include/common/bl_common.h 2819.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h 2820.. _Firmware Design: firmware-design.rst 2821.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 2822.. _plat/arm/board/fvp/fvp_pm.c: ../plat/arm/board/fvp/fvp_pm.c 2823.. _Platform compatibility policy: ./platform-compatibility-policy.rst 2824.. _IMF Design Guide: interrupt-framework-design.rst 2825.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 2826.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 2827.. _FreeBSD: https://www.freebsd.org 2828.. _SCC: http://www.simple-cc.org/ 2829