1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <cortex_a57.h> 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/psci/psci.h> 14 #include <plat/common/platform.h> 15 16 #include <bpmp.h> 17 #include <flowctrl.h> 18 #include <pmc.h> 19 #include <platform_def.h> 20 #include <security_engine.h> 21 #include <tegra_def.h> 22 #include <tegra_private.h> 23 #include <tegra_platform.h> 24 25 /* 26 * Register used to clear CPU reset signals. Each CPU has two reset 27 * signals: CPU reset (3:0) and Core reset (19:16). 28 */ 29 #define CPU_CMPLX_RESET_CLR 0x454 30 #define CPU_CORE_RESET_MASK 0x10001 31 32 /* Clock and Reset controller registers for system clock's settings */ 33 #define SCLK_RATE 0x30 34 #define SCLK_BURST_POLICY 0x28 35 #define SCLK_BURST_POLICY_DEFAULT 0x10000000 36 37 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 38 39 int32_t tegra_soc_validate_power_state(unsigned int power_state, 40 psci_power_state_t *req_state) 41 { 42 int state_id = psci_get_pstate_id(power_state); 43 44 /* Sanity check the requested state id */ 45 switch (state_id) { 46 case PSTATE_ID_CORE_POWERDN: 47 /* 48 * Core powerdown request only for afflvl 0 49 */ 50 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; 51 52 break; 53 54 case PSTATE_ID_CLUSTER_IDLE: 55 case PSTATE_ID_CLUSTER_POWERDN: 56 /* 57 * Cluster powerdown/idle request only for afflvl 1 58 */ 59 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 60 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; 61 62 break; 63 64 case PSTATE_ID_SOC_POWERDN: 65 /* 66 * System powerdown request only for afflvl 2 67 */ 68 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 69 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 70 71 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 72 PLAT_SYS_SUSPEND_STATE_ID; 73 74 break; 75 76 default: 77 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 78 return PSCI_E_INVALID_PARAMS; 79 } 80 81 return PSCI_E_SUCCESS; 82 } 83 84 /******************************************************************************* 85 * Platform handler to calculate the proper target power level at the 86 * specified affinity level 87 ******************************************************************************/ 88 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 89 const plat_local_state_t *states, 90 unsigned int ncpu) 91 { 92 plat_local_state_t target = PSCI_LOCAL_STATE_RUN; 93 int cpu = plat_my_core_pos(); 94 int core_pos = read_mpidr() & MPIDR_CPU_MASK; 95 uint32_t bpmp_reply, data[3]; 96 int ret; 97 98 /* get the power state at this level */ 99 if (lvl == MPIDR_AFFLVL1) 100 target = *(states + core_pos); 101 if (lvl == MPIDR_AFFLVL2) 102 target = *(states + cpu); 103 104 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { 105 106 /* initialize the bpmp interface */ 107 ret = tegra_bpmp_init(); 108 if (ret != 0U) { 109 110 /* Cluster idle not allowed */ 111 target = PSCI_LOCAL_STATE_RUN; 112 } else { 113 114 /* Cluster idle */ 115 data[0] = (uint32_t)cpu; 116 data[1] = TEGRA_PM_CC6; 117 data[2] = TEGRA_PM_SC1; 118 ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, 119 (void *)&data, (int)sizeof(data), 120 (void *)&bpmp_reply, 121 (int)sizeof(bpmp_reply)); 122 123 /* check if cluster idle entry is allowed */ 124 if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { 125 126 /* Cluster idle not allowed */ 127 target = PSCI_LOCAL_STATE_RUN; 128 } 129 } 130 131 } else if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_POWERDN)) { 132 133 /* initialize the bpmp interface */ 134 ret = tegra_bpmp_init(); 135 if (ret != 0U) { 136 137 /* Cluster power down not allowed */ 138 target = PSCI_LOCAL_STATE_RUN; 139 } else { 140 141 /* Cluster power-down */ 142 data[0] = (uint32_t)cpu; 143 data[1] = TEGRA_PM_CC7; 144 data[2] = TEGRA_PM_SC1; 145 ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, 146 (void *)&data, (int)sizeof(data), 147 (void *)&bpmp_reply, 148 (int)sizeof(bpmp_reply)); 149 150 /* check if cluster power down is allowed */ 151 if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { 152 153 /* Cluster power down not allowed */ 154 target = PSCI_LOCAL_STATE_RUN; 155 } 156 } 157 158 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && 159 (target == PSTATE_ID_SOC_POWERDN)) { 160 161 /* System Suspend */ 162 target = PSTATE_ID_SOC_POWERDN; 163 164 } else { 165 ; /* do nothing */ 166 } 167 168 return target; 169 } 170 171 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 172 { 173 u_register_t mpidr = read_mpidr(); 174 const plat_local_state_t *pwr_domain_state = 175 target_state->pwr_domain_state; 176 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; 177 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; 178 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; 179 int ret = PSCI_E_SUCCESS; 180 181 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 182 183 assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || 184 (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); 185 assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || 186 (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); 187 188 if (tegra_chipid_is_t210_b01()) { 189 190 /* Suspend se/se2 and pka1 */ 191 if (tegra_se_suspend() != 0) { 192 ret = PSCI_E_INTERN_FAIL; 193 } 194 } 195 196 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { 197 198 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); 199 200 /* Prepare for cluster idle */ 201 tegra_fc_cluster_idle(mpidr); 202 203 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) { 204 205 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); 206 207 /* Prepare for cluster powerdn */ 208 tegra_fc_cluster_powerdn(mpidr); 209 210 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 211 212 /* Prepare for cpu powerdn */ 213 tegra_fc_cpu_powerdn(mpidr); 214 215 } else { 216 ERROR("%s: Unknown state id (%d, %d, %d)\n", __func__, 217 stateid_afflvl2, stateid_afflvl1, stateid_afflvl0); 218 ret = PSCI_E_NOT_SUPPORTED; 219 } 220 221 return ret; 222 } 223 224 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 225 { 226 u_register_t mpidr = read_mpidr(); 227 const plat_local_state_t *pwr_domain_state = 228 target_state->pwr_domain_state; 229 unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL]; 230 231 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 232 233 if (tegra_chipid_is_t210_b01()) { 234 /* Save tzram contents */ 235 tegra_se_save_tzram(); 236 } 237 238 /* enter system suspend */ 239 tegra_fc_soc_powerdn(mpidr); 240 } 241 242 return PSCI_E_SUCCESS; 243 } 244 245 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 246 { 247 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 248 uint32_t val; 249 250 /* platform parameter passed by the previous bootloader */ 251 if (plat_params->l2_ecc_parity_prot_dis != 1) { 252 /* Enable ECC Parity Protection for Cortex-A57 CPUs */ 253 val = read_l2ctlr_el1(); 254 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 255 write_l2ctlr_el1(val); 256 } 257 258 /* 259 * Check if we are exiting from SOC_POWERDN. 260 */ 261 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 262 PLAT_SYS_SUSPEND_STATE_ID) { 263 264 /* 265 * Security engine resume 266 */ 267 if (tegra_chipid_is_t210_b01()) { 268 tegra_se_resume(); 269 } 270 271 /* 272 * Lock scratch registers which hold the CPU vectors 273 */ 274 tegra_pmc_lock_cpu_vectors(); 275 276 /* 277 * Enable WRAP to INCR burst type conversions for 278 * incoming requests on the AXI slave ports. 279 */ 280 val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); 281 val &= ~ENABLE_UNSUP_TX_ERRORS; 282 val |= ENABLE_WRAP_TO_INCR_BURSTS; 283 mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); 284 285 /* 286 * Restore Boot and Power Management Processor (BPMP) reset 287 * address and reset it. 288 */ 289 tegra_fc_reset_bpmp(); 290 } 291 292 /* 293 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 294 * used for power management and boot purposes. Inform the BPMP that 295 * we have completed the cluster power up. 296 */ 297 tegra_fc_lock_active_cluster(); 298 299 return PSCI_E_SUCCESS; 300 } 301 302 int tegra_soc_pwr_domain_on(u_register_t mpidr) 303 { 304 int cpu = mpidr & MPIDR_CPU_MASK; 305 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 306 307 /* Deassert CPU reset signals */ 308 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 309 310 /* Turn on CPU using flow controller or PMC */ 311 if (cpu_powergate_mask[cpu] == 0) { 312 tegra_pmc_cpu_on(cpu); 313 cpu_powergate_mask[cpu] = 1; 314 } else { 315 tegra_fc_cpu_on(cpu); 316 } 317 318 return PSCI_E_SUCCESS; 319 } 320 321 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 322 { 323 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); 324 return PSCI_E_SUCCESS; 325 } 326 327 int tegra_soc_prepare_system_reset(void) 328 { 329 /* 330 * Set System Clock (SCLK) to POR default so that the clock source 331 * for the PMC APB clock would not be changed due to system reset. 332 */ 333 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, 334 SCLK_BURST_POLICY_DEFAULT); 335 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); 336 337 /* Wait 1 ms to make sure clock source/device logic is stabilized. */ 338 mdelay(1); 339 340 return PSCI_E_SUCCESS; 341 } 342