1# 2# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# platform configs 8ENABLE_CONSOLE_SPE := 1 9$(eval $(call add_define,ENABLE_CONSOLE_SPE)) 10 11ENABLE_STRICT_CHECKING_MODE := 1 12$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE)) 13 14USE_GPC_DMA := 1 15$(eval $(call add_define,USE_GPC_DMA)) 16 17RESET_TO_BL31 := 1 18 19PROGRAMMABLE_RESET_ADDRESS := 1 20 21COLD_BOOT_SINGLE_CPU := 1 22 23# platform settings 24TZDRAM_BASE := 0x40000000 25$(eval $(call add_define,TZDRAM_BASE)) 26 27MAX_XLAT_TABLES := 25 28$(eval $(call add_define,MAX_XLAT_TABLES)) 29 30MAX_MMAP_REGIONS := 30 31$(eval $(call add_define,MAX_MMAP_REGIONS)) 32 33# enable RAS handling 34HANDLE_EA_EL3_FIRST := 1 35RAS_EXTENSION := 1 36 37# platform files 38PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \ 39 -I${SOC_DIR}/drivers/include 40 41BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ 42 lib/cpus/aarch64/denver.S \ 43 ${COMMON_DIR}/drivers/bpmp_ipc/intf.c \ 44 ${COMMON_DIR}/drivers/bpmp_ipc/ivc.c \ 45 ${COMMON_DIR}/drivers/gpcdma/gpcdma.c \ 46 ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ 47 ${COMMON_DIR}/drivers/smmu/smmu.c \ 48 ${SOC_DIR}/drivers/mce/mce.c \ 49 ${SOC_DIR}/drivers/mce/nvg.c \ 50 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ 51 ${SOC_DIR}/drivers/se/se.c \ 52 ${SOC_DIR}/plat_memctrl.c \ 53 ${SOC_DIR}/plat_psci_handlers.c \ 54 ${SOC_DIR}/plat_setup.c \ 55 ${SOC_DIR}/plat_secondary.c \ 56 ${SOC_DIR}/plat_sip_calls.c \ 57 ${SOC_DIR}/plat_smmu.c \ 58 ${SOC_DIR}/plat_trampoline.S 59 60ifeq (${ENABLE_CONSOLE_SPE},1) 61BL31_SOURCES += ${COMMON_DIR}/drivers/spe/shared_console.S 62endif 63 64# RAS sources 65ifeq (${RAS_EXTENSION},1) 66BL31_SOURCES += lib/extensions/ras/std_err_record.c \ 67 lib/extensions/ras/ras_common.c \ 68 ${SOC_DIR}/plat_ras.c 69endif 70