1/* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <common/bl_common.ld.h> 8#include <lib/xlat_tables/xlat_tables_defs.h> 9 10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12ENTRY(bl2_entrypoint) 13 14MEMORY { 15#if BL2_IN_XIP_MEM 16 ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE 17 RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE 18#else 19 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE 20#endif 21} 22 23#if !BL2_IN_XIP_MEM 24#define ROM RAM 25#endif 26 27SECTIONS 28{ 29#if BL2_IN_XIP_MEM 30 . = BL2_RO_BASE; 31 ASSERT(. == ALIGN(PAGE_SIZE), 32 "BL2_RO_BASE address is not aligned on a page boundary.") 33#else 34 . = BL2_BASE; 35 ASSERT(. == ALIGN(PAGE_SIZE), 36 "BL2_BASE address is not aligned on a page boundary.") 37#endif 38 39#if SEPARATE_CODE_AND_RODATA 40 .text . : { 41 __TEXT_START__ = .; 42 __TEXT_RESIDENT_START__ = .; 43 *bl2_el3_entrypoint.o(.text*) 44 *(.text.asm.*) 45 __TEXT_RESIDENT_END__ = .; 46 *(SORT_BY_ALIGNMENT(.text*)) 47 *(.vectors) 48 . = ALIGN(PAGE_SIZE); 49 __TEXT_END__ = .; 50 } >ROM 51 52 .rodata . : { 53 __RODATA_START__ = .; 54 *(SORT_BY_ALIGNMENT(.rodata*)) 55 56 RODATA_COMMON 57 58 . = ALIGN(PAGE_SIZE); 59 __RODATA_END__ = .; 60 } >ROM 61 62 ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE, 63 "Resident part of BL2 has exceeded its limit.") 64#else 65 ro . : { 66 __RO_START__ = .; 67 __TEXT_RESIDENT_START__ = .; 68 *bl2_el3_entrypoint.o(.text*) 69 *(.text.asm.*) 70 __TEXT_RESIDENT_END__ = .; 71 *(SORT_BY_ALIGNMENT(.text*)) 72 *(SORT_BY_ALIGNMENT(.rodata*)) 73 74 RODATA_COMMON 75 76 *(.vectors) 77 __RO_END_UNALIGNED__ = .; 78 /* 79 * Memory page(s) mapped to this section will be marked as 80 * read-only, executable. No RW data from the next section must 81 * creep in. Ensure the rest of the current memory page is unused. 82 */ 83 . = ALIGN(PAGE_SIZE); 84 85 __RO_END__ = .; 86 } >ROM 87#endif 88 89 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 90 "cpu_ops not defined for this platform.") 91 92#if BL2_IN_XIP_MEM 93 . = BL2_RW_BASE; 94 ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE), 95 "BL2_RW_BASE address is not aligned on a page boundary.") 96#endif 97 98 /* 99 * Define a linker symbol to mark start of the RW memory area for this 100 * image. 101 */ 102 __RW_START__ = . ; 103 104 DATA_SECTION >RAM AT>ROM 105 __DATA_RAM_START__ = __DATA_START__; 106 __DATA_RAM_END__ = __DATA_END__; 107 108 /* 109 * .rela.dyn needs to come after .data for the read-elf utility to parse 110 * this section correctly. Ensure 8-byte alignment so that the fields of 111 * RELA data structure are aligned. 112 */ 113 . = ALIGN(8); 114 __RELA_START__ = .; 115 .rela.dyn . : { 116 } >RAM 117 __RELA_END__ = .; 118 119 STACK_SECTION >RAM 120 BSS_SECTION >RAM 121 XLAT_TABLE_SECTION >RAM 122 123#if USE_COHERENT_MEM 124 /* 125 * The base address of the coherent memory section must be page-aligned (4K) 126 * to guarantee that the coherent data are stored on their own pages and 127 * are not mixed with normal data. This is required to set up the correct 128 * memory attributes for the coherent data page tables. 129 */ 130 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 131 __COHERENT_RAM_START__ = .; 132 *(tzfw_coherent_mem) 133 __COHERENT_RAM_END_UNALIGNED__ = .; 134 /* 135 * Memory page(s) mapped to this section will be marked 136 * as device memory. No other unexpected data must creep in. 137 * Ensure the rest of the current memory page is unused. 138 */ 139 . = ALIGN(PAGE_SIZE); 140 __COHERENT_RAM_END__ = .; 141 } >RAM 142#endif 143 144 /* 145 * Define a linker symbol to mark end of the RW memory area for this 146 * image. 147 */ 148 __RW_END__ = .; 149 __BL2_END__ = .; 150 151 /DISCARD/ : { 152 *(.dynsym .dynstr .hash .gnu.hash) 153 } 154 155#if BL2_IN_XIP_MEM 156 __BL2_RAM_START__ = ADDR(.data); 157 __BL2_RAM_END__ = .; 158 159 __DATA_ROM_START__ = LOADADDR(.data); 160 __DATA_SIZE__ = SIZEOF(.data); 161 162 /* 163 * The .data section is the last PROGBITS section so its end marks the end 164 * of BL2's RO content in XIP memory.. 165 */ 166 __BL2_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 167 ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT, 168 "BL2's RO content has exceeded its limit.") 169#endif 170 __BSS_SIZE__ = SIZEOF(.bss); 171 172 173#if USE_COHERENT_MEM 174 __COHERENT_RAM_UNALIGNED_SIZE__ = 175 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 176#endif 177 178#if BL2_IN_XIP_MEM 179 ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.") 180#else 181 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") 182#endif 183} 184