1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <bl31/bl31.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/common/platform.h> 16 17 #include <plat_private.h> 18 19 #define BL31_END (unsigned long)(&__BL31_END__) 20 21 static entry_point_info_t bl32_image_ep_info; 22 static entry_point_info_t bl33_image_ep_info; 23 24 /* 25 * Return a pointer to the 'entry_point_info' structure of the next image for 26 * the security state specified. BL33 corresponds to the non-secure image type 27 * while BL32 corresponds to the secure image type. A NULL pointer is returned 28 * if the image does not exist. 29 */ 30 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 31 { 32 assert(sec_state_is_valid(type)); 33 34 if (type == NON_SECURE) 35 return &bl33_image_ep_info; 36 37 return &bl32_image_ep_info; 38 } 39 40 /* 41 * Set the build time defaults. We want to do this when doing a JTAG boot 42 * or if we can't find any other config data. 43 */ 44 static inline void bl31_set_default_config(void) 45 { 46 bl32_image_ep_info.pc = BL32_BASE; 47 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 48 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 49 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 50 DISABLE_ALL_EXCEPTIONS); 51 } 52 53 /* 54 * Perform any BL31 specific platform actions. Here is an opportunity to copy 55 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 56 * are lost (potentially). This needs to be done before the MMU is initialized 57 * so that the memory layout can be used while creating page tables. 58 */ 59 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 60 u_register_t arg2, u_register_t arg3) 61 { 62 /* Initialize the console to provide early debug support */ 63 console_init(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(), 64 ZYNQMP_UART_BAUDRATE); 65 66 /* Initialize the platform config for future decision making */ 67 zynqmp_config_setup(); 68 69 /* There are no parameters from BL2 if BL31 is a reset vector */ 70 assert(arg0 == 0U); 71 assert(arg1 == 0U); 72 73 /* 74 * Do initial security configuration to allow DRAM/device access. On 75 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 76 * other platforms might have more programmable security devices 77 * present. 78 */ 79 80 /* Populate common information for BL32 and BL33 */ 81 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 82 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 83 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 84 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 85 86 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 87 bl31_set_default_config(); 88 } else { 89 /* use parameters from FSBL */ 90 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, 91 &bl33_image_ep_info); 92 if (ret == FSBL_HANDOFF_NO_STRUCT) 93 bl31_set_default_config(); 94 else if (ret != FSBL_HANDOFF_SUCCESS) 95 panic(); 96 } 97 98 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 99 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 100 } 101 102 /* Enable the test setup */ 103 #ifndef ZYNQMP_TESTING 104 static void zynqmp_testing_setup(void) { } 105 #else 106 static void zynqmp_testing_setup(void) 107 { 108 uint32_t actlr_el3, actlr_el2; 109 110 /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */ 111 actlr_el3 = read_actlr_el3(); 112 actlr_el2 = read_actlr_el2(); 113 114 actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 115 actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 116 write_actlr_el3(actlr_el3); 117 write_actlr_el2(actlr_el2); 118 } 119 #endif 120 121 #if ZYNQMP_WDT_RESTART 122 static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3]; 123 124 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 125 { 126 /* Validate 'handler' and 'id' parameters */ 127 if (!handler || id >= MAX_INTR_EL3) 128 return -EINVAL; 129 130 /* Check if a handler has already been registered */ 131 if (type_el3_interrupt_table[id]) 132 return -EALREADY; 133 134 type_el3_interrupt_table[id] = handler; 135 136 return 0; 137 } 138 139 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 140 void *handle, void *cookie) 141 { 142 uint32_t intr_id; 143 interrupt_type_handler_t handler; 144 145 intr_id = plat_ic_get_pending_interrupt_id(); 146 handler = type_el3_interrupt_table[intr_id]; 147 if (handler != NULL) 148 handler(intr_id, flags, handle, cookie); 149 150 return 0; 151 } 152 #endif 153 154 void bl31_platform_setup(void) 155 { 156 /* Initialize the gic cpu and distributor interfaces */ 157 plat_arm_gic_driver_init(); 158 plat_arm_gic_init(); 159 zynqmp_testing_setup(); 160 } 161 162 void bl31_plat_runtime_setup(void) 163 { 164 #if ZYNQMP_WDT_RESTART 165 uint64_t flags = 0; 166 uint64_t rc; 167 168 set_interrupt_rm_flag(flags, NON_SECURE); 169 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 170 rdo_el3_interrupt_handler, flags); 171 if (rc) 172 panic(); 173 #endif 174 } 175 176 /* 177 * Perform the very early platform specific architectural setup here. 178 */ 179 void bl31_plat_arch_setup(void) 180 { 181 plat_arm_interconnect_init(); 182 plat_arm_interconnect_enter_coherency(); 183 184 185 const mmap_region_t bl_regions[] = { 186 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 187 MT_MEMORY | MT_RW | MT_SECURE), 188 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 189 MT_CODE | MT_SECURE), 190 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 191 MT_RO_DATA | MT_SECURE), 192 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 193 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 194 MT_DEVICE | MT_RW | MT_SECURE), 195 {0} 196 }; 197 198 setup_page_tables(bl_regions, plat_arm_get_mmap()); 199 enable_mmu_el3(0); 200 } 201