1/* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#ifndef EL3_COMMON_MACROS_S 8#define EL3_COMMON_MACROS_S 9 10#include <arch.h> 11#include <asm_macros.S> 12#include <assert_macros.S> 13 14 /* 15 * Helper macro to initialise EL3 registers we care about. 16 */ 17 .macro el3_arch_init_common 18 /* --------------------------------------------------------------------- 19 * SCTLR has already been initialised - read current value before 20 * modifying. 21 * 22 * SCTLR.I: Enable the instruction cache. 23 * 24 * SCTLR.A: Enable Alignment fault checking. All instructions that load 25 * or store one or more registers have an alignment check that the 26 * address being accessed is aligned to the size of the data element(s) 27 * being accessed. 28 * --------------------------------------------------------------------- 29 */ 30 ldr r1, =(SCTLR_I_BIT | SCTLR_A_BIT) 31 ldcopr r0, SCTLR 32 orr r0, r0, r1 33 stcopr r0, SCTLR 34 isb 35 36 /* --------------------------------------------------------------------- 37 * Initialise SCR, setting all fields rather than relying on the hw. 38 * 39 * SCR.SIF: Enabled so that Secure state instruction fetches from 40 * Non-secure memory are not permitted. 41 * --------------------------------------------------------------------- 42 */ 43 ldr r0, =(SCR_RESET_VAL | SCR_SIF_BIT) 44 stcopr r0, SCR 45 46 /* ----------------------------------------------------- 47 * Enable the Asynchronous data abort now that the 48 * exception vectors have been setup. 49 * ----------------------------------------------------- 50 */ 51 cpsie a 52 isb 53 54 /* --------------------------------------------------------------------- 55 * Initialise NSACR, setting all the fields, except for the 56 * IMPLEMENTATION DEFINED field, rather than relying on the hw. Some 57 * fields are architecturally UNKNOWN on reset. 58 * 59 * NSACR_ENABLE_FP_ACCESS: Represents NSACR.cp11 and NSACR.cp10. The 60 * cp11 field is ignored, but is set to same value as cp10. The cp10 61 * field is set to allow access to Advanced SIMD and floating point 62 * features from both Security states. 63 * --------------------------------------------------------------------- 64 */ 65 ldcopr r0, NSACR 66 and r0, r0, #NSACR_IMP_DEF_MASK 67 orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS) 68 stcopr r0, NSACR 69 isb 70 71 /* --------------------------------------------------------------------- 72 * Initialise CPACR, setting all fields rather than relying on hw. Some 73 * fields are architecturally UNKNOWN on reset. 74 * 75 * CPACR.TRCDIS: Trap control for PL0 and PL1 System register accesses 76 * to trace registers. Set to zero to allow access. 77 * 78 * CPACR_ENABLE_FP_ACCESS: Represents CPACR.cp11 and CPACR.cp10. The 79 * cp11 field is ignored, but is set to same value as cp10. The cp10 80 * field is set to allow full access from PL0 and PL1 to floating-point 81 * and Advanced SIMD features. 82 * --------------------------------------------------------------------- 83 */ 84 ldr r0, =((CPACR_RESET_VAL | CPACR_ENABLE_FP_ACCESS) & ~(TRCDIS_BIT)) 85 stcopr r0, CPACR 86 isb 87 88 /* --------------------------------------------------------------------- 89 * Initialise FPEXC, setting all fields rather than relying on hw. Some 90 * fields are architecturally UNKNOWN on reset and are set to zero 91 * except for field(s) listed below. 92 * 93 * FPEXC.EN: Enable access to Advanced SIMD and floating point features 94 * from all exception levels. 95 * --------------------------------------------------------------------- 96 */ 97#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_VFP) 98 ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT) 99 vmsr FPEXC, r0 100 isb 101#endif 102 103#if (ARM_ARCH_MAJOR > 7) 104 /* --------------------------------------------------------------------- 105 * Initialise SDCR, setting all the fields rather than relying on hw. 106 * 107 * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from 108 * Secure EL1 are disabled. 109 * 110 * SDCR: Set to one so that cycle counting by PMCCNTR is prohibited in 111 * Secure state. This bit is RES0 in versions of the architecture 112 * earlier than ARMv8.5, setting it to 1 doesn't have any effect on 113 * them. 114 * --------------------------------------------------------------------- 115 */ 116 ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE) | SDCR_SCCD_BIT) 117 stcopr r0, SDCR 118#endif 119 120 /* 121 * If Data Independent Timing (DIT) functionality is implemented, 122 * always enable DIT in EL3 123 */ 124 ldcopr r0, ID_PFR0 125 and r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT) 126 cmp r0, #ID_PFR0_DIT_SUPPORTED 127 bne 1f 128 mrs r0, cpsr 129 orr r0, r0, #CPSR_DIT_BIT 130 msr cpsr_cxsf, r0 1311: 132 .endm 133 134/* ----------------------------------------------------------------------------- 135 * This is the super set of actions that need to be performed during a cold boot 136 * or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN). 137 * 138 * This macro will always perform reset handling, architectural initialisations 139 * and stack setup. The rest of the actions are optional because they might not 140 * be needed, depending on the context in which this macro is called. This is 141 * why this macro is parameterised ; each parameter allows to enable/disable 142 * some actions. 143 * 144 * _init_sctlr: 145 * Whether the macro needs to initialise the SCTLR register including 146 * configuring the endianness of data accesses. 147 * 148 * _warm_boot_mailbox: 149 * Whether the macro needs to detect the type of boot (cold/warm). The 150 * detection is based on the platform entrypoint address : if it is zero 151 * then it is a cold boot, otherwise it is a warm boot. In the latter case, 152 * this macro jumps on the platform entrypoint address. 153 * 154 * _secondary_cold_boot: 155 * Whether the macro needs to identify the CPU that is calling it: primary 156 * CPU or secondary CPU. The primary CPU will be allowed to carry on with 157 * the platform initialisations, while the secondaries will be put in a 158 * platform-specific state in the meantime. 159 * 160 * If the caller knows this macro will only be called by the primary CPU 161 * then this parameter can be defined to 0 to skip this step. 162 * 163 * _init_memory: 164 * Whether the macro needs to initialise the memory. 165 * 166 * _init_c_runtime: 167 * Whether the macro needs to initialise the C runtime environment. 168 * 169 * _exception_vectors: 170 * Address of the exception vectors to program in the VBAR_EL3 register. 171 * ----------------------------------------------------------------------------- 172 */ 173 .macro el3_entrypoint_common \ 174 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ 175 _init_memory, _init_c_runtime, _exception_vectors 176 177 /* Make sure we are in Secure Mode */ 178#if ENABLE_ASSERTIONS 179 ldcopr r0, SCR 180 tst r0, #SCR_NS_BIT 181 ASM_ASSERT(eq) 182#endif 183 184 .if \_init_sctlr 185 /* ------------------------------------------------------------- 186 * This is the initialisation of SCTLR and so must ensure that 187 * all fields are explicitly set rather than relying on hw. Some 188 * fields reset to an IMPLEMENTATION DEFINED value. 189 * 190 * SCTLR.TE: Set to zero so that exceptions to an Exception 191 * Level executing at PL1 are taken to A32 state. 192 * 193 * SCTLR.EE: Set the CPU endianness before doing anything that 194 * might involve memory reads or writes. Set to zero to select 195 * Little Endian. 196 * 197 * SCTLR.V: Set to zero to select the normal exception vectors 198 * with base address held in VBAR. 199 * 200 * SCTLR.DSSBS: Set to zero to disable speculation store bypass 201 * safe behaviour upon exception entry to EL3. 202 * ------------------------------------------------------------- 203 */ 204 ldr r0, =(SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_EE_BIT | \ 205 SCTLR_V_BIT | SCTLR_DSSBS_BIT)) 206 stcopr r0, SCTLR 207 isb 208 .endif /* _init_sctlr */ 209 210 /* Switch to monitor mode */ 211 cps #MODE32_mon 212 isb 213 214 .if \_warm_boot_mailbox 215 /* ------------------------------------------------------------- 216 * This code will be executed for both warm and cold resets. 217 * Now is the time to distinguish between the two. 218 * Query the platform entrypoint address and if it is not zero 219 * then it means it is a warm boot so jump to this address. 220 * ------------------------------------------------------------- 221 */ 222 bl plat_get_my_entrypoint 223 cmp r0, #0 224 bxne r0 225 .endif /* _warm_boot_mailbox */ 226 227 /* --------------------------------------------------------------------- 228 * Set the exception vectors (VBAR/MVBAR). 229 * --------------------------------------------------------------------- 230 */ 231 ldr r0, =\_exception_vectors 232 stcopr r0, VBAR 233 stcopr r0, MVBAR 234 isb 235 236 /* --------------------------------------------------------------------- 237 * It is a cold boot. 238 * Perform any processor specific actions upon reset e.g. cache, TLB 239 * invalidations etc. 240 * --------------------------------------------------------------------- 241 */ 242 bl reset_handler 243 244 el3_arch_init_common 245 246 .if \_secondary_cold_boot 247 /* ------------------------------------------------------------- 248 * Check if this is a primary or secondary CPU cold boot. 249 * The primary CPU will set up the platform while the 250 * secondaries are placed in a platform-specific state until the 251 * primary CPU performs the necessary actions to bring them out 252 * of that state and allows entry into the OS. 253 * ------------------------------------------------------------- 254 */ 255 bl plat_is_my_cpu_primary 256 cmp r0, #0 257 bne do_primary_cold_boot 258 259 /* This is a cold boot on a secondary CPU */ 260 bl plat_secondary_cold_boot_setup 261 /* plat_secondary_cold_boot_setup() is not supposed to return */ 262 no_ret plat_panic_handler 263 264 do_primary_cold_boot: 265 .endif /* _secondary_cold_boot */ 266 267 /* --------------------------------------------------------------------- 268 * Initialize memory now. Secondary CPU initialization won't get to this 269 * point. 270 * --------------------------------------------------------------------- 271 */ 272 273 .if \_init_memory 274 bl platform_mem_init 275 .endif /* _init_memory */ 276 277 /* --------------------------------------------------------------------- 278 * Init C runtime environment: 279 * - Zero-initialise the NOBITS sections. There are 2 of them: 280 * - the .bss section; 281 * - the coherent memory section (if any). 282 * - Relocate the data section from ROM to RAM, if required. 283 * --------------------------------------------------------------------- 284 */ 285 .if \_init_c_runtime 286#if defined(IMAGE_BL32) || (defined(IMAGE_BL2) && BL2_AT_EL3) 287 /* ----------------------------------------------------------------- 288 * Invalidate the RW memory used by the image. This 289 * includes the data and NOBITS sections. This is done to 290 * safeguard against possible corruption of this memory by 291 * dirty cache lines in a system cache as a result of use by 292 * an earlier boot loader stage. 293 * ----------------------------------------------------------------- 294 */ 295 ldr r0, =__RW_START__ 296 ldr r1, =__RW_END__ 297 sub r1, r1, r0 298 bl inv_dcache_range 299#endif 300 301 ldr r0, =__BSS_START__ 302 ldr r1, =__BSS_SIZE__ 303 bl zeromem 304 305#if USE_COHERENT_MEM 306 ldr r0, =__COHERENT_RAM_START__ 307 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ 308 bl zeromem 309#endif 310 311#ifdef IMAGE_BL1 312 /* ----------------------------------------------------- 313 * Copy data from ROM to RAM. 314 * ----------------------------------------------------- 315 */ 316 ldr r0, =__DATA_RAM_START__ 317 ldr r1, =__DATA_ROM_START__ 318 ldr r2, =__DATA_SIZE__ 319 bl memcpy4 320#endif 321 .endif /* _init_c_runtime */ 322 323 /* --------------------------------------------------------------------- 324 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when 325 * the MMU is enabled. There is no risk of reading stale stack memory 326 * after enabling the MMU as only the primary CPU is running at the 327 * moment. 328 * --------------------------------------------------------------------- 329 */ 330 bl plat_set_my_stack 331 332#if STACK_PROTECTOR_ENABLED 333 .if \_init_c_runtime 334 bl update_stack_protector_canary 335 .endif /* _init_c_runtime */ 336#endif 337 .endm 338 339#endif /* EL3_COMMON_MACROS_S */ 340