| 55ab8f06 | 27-Feb-2024 |
Alvin Chang <alvinga@andestech.com> |
core: Refactor console_init() and introduce plat_console_init()
Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console
core: Refactor console_init() and introduce plat_console_init()
Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console drivers (e.g., semihosting console).
If the cross-platform console drivers are not configured to be compiled,
plat_console_init() will be invoked to initialize platform-specific
console driver.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
show more ...
|
| 8c578243 | 22-Nov-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
plat-zynq7k: use gic_init_per_cpu()
Call gic_init_per_cpu() instead of the now deprecated gic_cpu_init().
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> |
| df913c6d | 02-Aug-2023 |
Alvin Chang <alvinga@andestech.com> |
core: arm: Rename primary_init_intc() to boot_primary_init_intc()
Since interrupt controllers are usually initialized in boot stage,
rename primary_init_intc() to boot_primary_init_intc().
Signed-o
core: arm: Rename primary_init_intc() to boot_primary_init_intc()
Since interrupt controllers are usually initialized in boot stage,
rename primary_init_intc() to boot_primary_init_intc().
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
show more ...
|
| 8aae4669 | 31-Jul-2023 |
Alvin Chang <alvinga@andestech.com> |
core: arm: Rename main_secondary_init_intc() to boot_secondary_init_intc()
main_secondary_*() is an ambiguous name since it conveys no meaning
relative to the purpose of the function. Fix it by rena
core: arm: Rename main_secondary_init_intc() to boot_secondary_init_intc()
main_secondary_*() is an ambiguous name since it conveys no meaning
relative to the purpose of the function. Fix it by renameing to
boot_secondary_init_intc(), since interrupt controllers are always
initialized in boot stage.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
show more ...
|
| ef50391e | 19-Jul-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: rename interrupt controller functions
This commit renames interrupt controller function names
to be more generic:
- Rename main_init_gic() to primary_init_intc()
- Rename secondary_init_gic()
core: rename interrupt controller functions
This commit renames interrupt controller function names
to be more generic:
- Rename main_init_gic() to primary_init_intc()
- Rename secondary_init_gic() to secondary_init_intc()
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
show more ...
|
| 67e55c51 | 16-May-2023 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: define main interrupt controller data from its driver
All but one platforms define CPU core interrupt controller from their
platform main.c source file next to its main interrupt handler.
This
core: define main interrupt controller data from its driver
All but one platforms define CPU core interrupt controller from their
platform main.c source file next to its main interrupt handler.
This change factorize these implementation by moving the definition
of the controller data instance straight in the controller driver
source file. This change makes each controller driver to implement
straight itr_core_handler() function, preventing a extra branch on
interrupt execution. Interrupt controller driver initialization
function now straight calls itr_core_init().
This changes treats case when CFG_CORE_WORKAROUND_ARM_NMFI is enable
to not conflict with core/arch/arm/kernel/thread.c that already
overrides itr_core_handler() weak implementation.
With this change, the main controller initialization function
(gic_init(), gic_init_base_addr(), gic_cpu_init() and hfic_init())
no more gets the controller data as input argument.
As a consequence, definition of struct hfic_data and struct gic_data
moves from their respective driver header file to the respective
driver source file.
As a consequence, gic_dump() no more requires an argument.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 217277de | 04-Sep-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
plat-zynq7k: Configure platform needing NMFI workaround
Unfortunately Xilinx Zynq-7000's ARM Cortext-A9 core has been configured
with NMFI support. This causes problems for OP-TEE's atomic context
p
plat-zynq7k: Configure platform needing NMFI workaround
Unfortunately Xilinx Zynq-7000's ARM Cortext-A9 core has been configured
with NMFI support. This causes problems for OP-TEE's atomic context
protections rendering FIQ interrupt un-usable in the system designs.
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 60801696 | 15-Feb-2022 |
Volodymyr Babchuk <volodymyr_babchuk@epam.com> |
plat: arm: refactor GIC initialization
All platforms (except STM32MP1) follow the same pattern during GIC
initialization: get virtual addresses for distributor (and optionally,
for CPU interface), c
plat: arm: refactor GIC initialization
All platforms (except STM32MP1) follow the same pattern during GIC
initialization: get virtual addresses for distributor (and optionally,
for CPU interface), check that they are not NULL, call either
gic_init() or gic_init_base_addr().
We can move most of this logic into gic_init_base_addr(), while
platform-specific code will supply only base physical addresses for
distributor and CPU interface. This will simplify and align platform
code.
ST32MP1 had more complex logic, as it used io_pa_or_va_secure() to get
MMIO range addresses. However, as main_init_gic() called
assert(cpu_mmu_enabled()), there is no sense in using
io_pa_or_va_secure(), because we already ensured that VA will be
always used. Thus assert() call was moved to gic_init_base_addr(), and
STM32MP1 were aligned with other platforms.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| c2e4eb43 | 23-May-2021 |
Anton Rybakov <a.rybakov@omp.ru> |
core_mmu: fix phys_to_virt() to check length
phys_to_virt() function without length parameter doesn`t
always have ability to find the correct mapping for
requested physical address. This is because
core_mmu: fix phys_to_virt() to check length
phys_to_virt() function without length parameter doesn`t
always have ability to find the correct mapping for
requested physical address. This is because physical
address can be mapped in the same time in different virtual
regions with different length. So the first found region
which contains the requested physical address possibly
doesn`t have enough mapped data. This is fixed by adding
the length parameter to phys_to_virt() function. Length
parameter can be set to 1 if caller knows that requested
(pa + len) doesn`t cross mapping granule boundary.
core_mmu_get_va() and io_pa_or_va() functions now are
take length parameter too as they based on phys_to_virt()
in case of MMU enabled.
Signed-off-by: Anton Rybakov <a.rybakov@omp.ru>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_DK2)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qpsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek)
show more ...
|
| a3cc9156 | 03-Jun-2021 |
Yan Yan <yan.yan@windriver.com> |
plat-zynq7k: fix wrong argument ordering in NS world unlocking
A defect was introduced in 3.5.0 where the register value and address
in io_write32 are displaced, which eventually led to failure swit
plat-zynq7k: fix wrong argument ordering in NS world unlocking
A defect was introduced in 3.5.0 where the register value and address
in io_write32 are displaced, which eventually led to failure switching
to NS world.
Fixes: af4c7f4b3ad2 ("zynq7k: upgrade from write32() to io_write32() and friends")
Signed-off-by: Yan Yan <yan.yan@windriver.com>
Tested-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 3513f961 | 03-Sep-2020 |
Jerome Forissier <jerome@forissier.org> |
arm32: fold UNWIND(.fnstart/.fnend) into the FUNC macros
This change applies to arm32 assembler sources.
Instead of using UNWIND(.fnstart) after FUNC or LOCAL_FUNC and
UNWIND(.fnend) before END_FUN
arm32: fold UNWIND(.fnstart/.fnend) into the FUNC macros
This change applies to arm32 assembler sources.
Instead of using UNWIND(.fnstart) after FUNC or LOCAL_FUNC and
UNWIND(.fnend) before END_FUNC, let's fold these statements into the
FUNC macros.
The .fnstart/.fnend directives mark the start and end of a function
with an unwind table entry (.ARM.exidx) and therefore a function
without them has no entry and cannot be unwound. This means that a
stack dump (on abort or panic) would stop when reaching such a
function.
As a result of this patch, a small number of functions now have an
entry in the unwind table when they had none before (the functions
which were using FUNC or LOCAL_FUNC but had no .fnstart/.fnend). It was
almost always a bug and this pacth only increases the size of the
.ARM.exidx section by a few bytes (tested on QEMU).
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 827be46c | 03-Sep-2020 |
Jerome Forissier <jerome@forissier.org> |
arm32: move the UNWIND() macro to <asm.S>
All the users of the UNWIND() macro include <asm.S> already, which is
therefore a good place to define this macro. Let's move it from
<kernel/unwind.h> to <
arm32: move the UNWIND() macro to <asm.S>
All the users of the UNWIND() macro include <asm.S> already, which is
therefore a good place to define this macro. Let's move it from
<kernel/unwind.h> to <asm.S>, remove a couple of duplicates in
assembler files, and drop the useless includes.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| f3721740 | 23-Jul-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: remove the unused PM stubs
Removes the PM stubs and all references to CFG_PM_STUBS.
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.o
core: remove the unused PM stubs
Removes the PM stubs and all references to CFG_PM_STUBS.
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 651d7537 | 07-Jun-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: remove boot_get_handlers()
struct thread_handlers is used to pass the entry functions
for different power management events. In practice only .cpu_on is used
and with the default function at t
core: remove boot_get_handlers()
struct thread_handlers is used to pass the entry functions
for different power management events. In practice only .cpu_on is used
and with the default function at that. In the ARMv7 case where the
secure monitor replaces TF-A not even that function entry is used.
Remove struct thread_handlers and boot_get_handlers(). When configured
with TF-A initialize thread_*_handler_ptr with __weak default functions.
The __weak default PM functions
- thread_cpu_off_handler()
- thread_cpu_suspend_handler()
- thread_cpu_resume_handler()
- thread_system_off_handler()
- thread_system_reset_handler()
can be overridden by platforms when needed.
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 35e770df | 04-Jun-2020 |
Jerome Forissier <jerome@forissier.org> |
Move CFG_WITH_STACK_CANARIES to global config file
All platforms but one (bcm-ns3) set CFG_WITH_STACK_CANARIES ?= y in
their configuration files. Move this flag to the global mk/config.mk
instead. N
Move CFG_WITH_STACK_CANARIES to global config file
All platforms but one (bcm-ns3) set CFG_WITH_STACK_CANARIES ?= y in
their configuration files. Move this flag to the global mk/config.mk
instead. Not sure it matters much, but in order to avoid any functional
change, CFG_WITH_STACK_CANARIES ?= n is added to plat-bcm/conf.mk.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 65401337 | 07-Jun-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: remove generic_ from generic_boot
Now that the CFG_GENERIC_BOOT configuration flag has been removed also
remove "generic_" prefix from and in the related files.
Acked-by: Etienne Carriere <et
core: remove generic_ from generic_boot
Now that the CFG_GENERIC_BOOT configuration flag has been removed also
remove "generic_" prefix from and in the related files.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| 0146c7ad | 07-Jun-2020 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: make generic boot mandatory
The OP-TEE booting has since quite some time been unified in the sense
that all platforms use CFG_GENERIC_BOOT=y. Make this configuration option
mandatory and remov
core: make generic boot mandatory
The OP-TEE booting has since quite some time been unified in the sense
that all platforms use CFG_GENERIC_BOOT=y. Make this configuration option
mandatory and remove the CFG_GENERIC_BOOT flag.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 665fa256 | 20-Nov-2019 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add plat_primary_init_early()
Adds plat_primary_init_early() which replaces plat_cpu_reset_late().
plat_cpu_reset_late() was called for each cpu, but
plat_primary_init_early() is only called o
core: add plat_primary_init_early()
Adds plat_primary_init_early() which replaces plat_cpu_reset_late().
plat_cpu_reset_late() was called for each cpu, but
plat_primary_init_early() is only called on the primary cpu.
In practice that's not a problem (except for plat-stm, more on that
later) since all the platform specific plat_cpu_reset_late() only does
something if get_core_pos() returns 0, that is on the primary cpu.
On plat-stm SCR is now updated in plat_cpu_reset_early() instead.
This patch is needed because ASLR may relocate OP-TEE to a virtual base
address which differs from the physical base address. This means that
it's not possible to execute C code before MMU has been enabled.
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| e9f46c74 | 13-Aug-2019 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: replace thread_nintr_handler_ptr with weak function
Removes registration of platform specific secure interrupt handler in
thread_nintr_handler_ptr. Instead a __weak overridable
itr_core_handle
core: replace thread_nintr_handler_ptr with weak function
Removes registration of platform specific secure interrupt handler in
thread_nintr_handler_ptr. Instead a __weak overridable
itr_core_handler() is provided. Platforms which expects to receive
secure interrupts must override the default function. The default
function calls panic() if called.
With this also nintr is removed from struct thread_handlers and
consequently all platforms are updated to stop using that field.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| 612791d0 | 13-Aug-2019 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: replace thread_fast_smc_handler_ptr with weak function
Removes registration of platform specific fast SMC entry function in
thread_fast_smc_handler_ptr. Instead a __weak overridable
tee_entry_
core: replace thread_fast_smc_handler_ptr with weak function
Removes registration of platform specific fast SMC entry function in
thread_fast_smc_handler_ptr. Instead a __weak overridable
tee_entry_fast() is provided. Platforms that need a special
tee_entry_fast() (currently on plat-zynq7k) provides their own
tee_entry_fast() instead which at the end should call __tee_entry_fast()
which does the generic fast call handling.
With this also fast_smc is removed from struct thread_handlers and
consequently all platforms are updated to stop using that field.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| 2dd2ca5f | 13-Aug-2019 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: replace thread_std_smc_handler_ptr with weak function
Removes registration of platform specific standard SMC entry function in
thread_std_smc_handler_ptr. Instead a __weak overridable tee_entr
core: replace thread_std_smc_handler_ptr with weak function
Removes registration of platform specific standard SMC entry function in
thread_std_smc_handler_ptr. Instead a __weak overridable tee_entry_std()
is provided. Platforms that need a special tee_entry_std() (currently on
some STM platform) provides their own tee_entry_std() instead which at
the end should call __tee_entry_std() which does the generic standard
call handling.
With this also std_smc is removed from struct thread_handlers and
consequently all platforms are updated to stop using that field.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| af4c7f4b | 12-Feb-2019 |
Etienne Carriere <etienne.carriere@linaro.org> |
zynq7k: upgrade from write32() to io_write32() and friends
Replace use of readX() and writeX() with io_readX() and io_writeX().
The former are about to be deprecated in favor to the later.
Signed-o
zynq7k: upgrade from write32() to io_write32() and friends
Replace use of readX() and writeX() with io_readX() and io_writeX().
The former are about to be deprecated in favor to the later.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| a5e82dc7 | 11-Feb-2019 |
Jerome Forissier <jerome.forissier@linaro.org> |
core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularity
Device memory registered via register_phys_mem() is currently rounded
up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LP
core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularity
Device memory registered via register_phys_mem() is currently rounded
up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LPAE). This is not
needed and possibly incorrect for SoCs that define I/O memory maps with
regions aligned on a small page (4 KiB), because using a larger
granularity could result in overlaps between secure and non-secure
mappings. This could cause issues depending on the type of memory
firewall used by the SoC and its configuration. In any case, memory
types other than MEM_AREA_IO_{SEC,NSEC} *can* be mapped with small page
granularity using register_phys_mem(), so the situation is a bit
inconsistent.
This commit removes the rounding by default and provides a new macro:
register_phys_mem_pgdir(). Platforms that still need to use PGDIR_SIZE
granularity (typically because it consumes less page table space) need
to replace register_phys_mem() by register_phys_mem_pgdir().
In order to avoid any functional change in platform code, all calls to
register_phys_mem() with device memory are replaced with
register_phys_mem_pgdir(). In addition, CORE_MMU_DEVICE_SIZE is removed
and replaced with CORE_MMU_PGDIR_SIZE since there is no unique mapping
size for device memory anymore.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| 9f1eec75 | 17-Dec-2018 |
Jerome Forissier <jerome.forissier@linaro.org> |
Factor out ta-targets from platform config
Platforms use the same basic pattern again and again:
ta-targets = ta_arm32
ifeq ($(CFG_ARM64_core),y)
ta-targets += ta_arm64
endif
Let's move this p
Factor out ta-targets from platform config
Platforms use the same basic pattern again and again:
ta-targets = ta_arm32
ifeq ($(CFG_ARM64_core),y)
ta-targets += ta_arm64
endif
Let's move this pattern to core/arch/arm/arm.mk, make it the default, and
cleanup the platform configuration files.
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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|
| 9460285e | 04-Jun-2018 |
Jerome Forissier <jerome.forissier@linaro.org> |
plat-*/conf.mk: use $(call force, ...) to set CFG_TEE_CORE_NB_CORE
Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depend
plat-*/conf.mk: use $(call force, ...) to set CFG_TEE_CORE_NB_CORE
Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depends on the hardware
configuration and should not be configurable at build time.
Therefore, use $(call force,CFG_TEE_CORE_NB_CORE,<value>) to set the
value.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
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