xref: /optee_os/core/arch/arm/plat-zynqmp/main.c (revision 2dd2ca5f39e6dd144a8be81f5e00badf79d362fe)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (c) 2016, Xilinx Inc.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright notice,
10  * this list of conditions and the following disclaimer.
11  *
12  * 2. Redistributions in binary form must reproduce the above copyright notice,
13  * this list of conditions and the following disclaimer in the documentation
14  * and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26  * POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <platform_config.h>
30 
31 #include <stdint.h>
32 #include <string.h>
33 
34 #include <drivers/gic.h>
35 #include <drivers/cdns_uart.h>
36 
37 #include <arm.h>
38 #include <console.h>
39 #include <kernel/generic_boot.h>
40 #include <kernel/pm_stubs.h>
41 #include <kernel/misc.h>
42 #include <kernel/tee_time.h>
43 #include <mm/core_memprot.h>
44 #include <tee/entry_fast.h>
45 #include <tee/entry_std.h>
46 #include <trace.h>
47 
48 static void main_fiq(void);
49 static struct gic_data gic_data;
50 static struct cdns_uart_data console_data;
51 
52 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
53 			ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
54 			CORE_MMU_PGDIR_SIZE);
55 
56 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
57 			ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE),
58 			CORE_MMU_PGDIR_SIZE);
59 
60 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
61 			ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE),
62 			CORE_MMU_PGDIR_SIZE);
63 
64 static const struct thread_handlers handlers = {
65 	.fast_smc = tee_entry_fast,
66 	.nintr = main_fiq,
67 #if defined(CFG_WITH_ARM_TRUSTED_FW)
68 	.cpu_on = cpu_on_handler,
69 	.cpu_off = pm_do_nothing,
70 	.cpu_suspend = pm_do_nothing,
71 	.cpu_resume = pm_do_nothing,
72 	.system_off = pm_do_nothing,
73 	.system_reset = pm_do_nothing,
74 #else
75 	.cpu_on = pm_panic,
76 	.cpu_off = pm_panic,
77 	.cpu_suspend = pm_panic,
78 	.cpu_resume = pm_panic,
79 	.system_off = pm_panic,
80 	.system_reset = pm_panic,
81 #endif
82 };
83 
84 const struct thread_handlers *generic_boot_get_handlers(void)
85 {
86 	return &handlers;
87 }
88 
89 void main_init_gic(void)
90 {
91 	vaddr_t gicc_base, gicd_base;
92 
93 	gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET,
94 					  MEM_AREA_IO_SEC);
95 	gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
96 					  MEM_AREA_IO_SEC);
97 	/* On ARMv8, GIC configuration is initialized in ARM-TF */
98 	gic_init_base_addr(&gic_data, gicc_base, gicd_base);
99 }
100 
101 static void main_fiq(void)
102 {
103 	gic_it_handle(&gic_data);
104 }
105 
106 void console_init(void)
107 {
108 	cdns_uart_init(&console_data, CONSOLE_UART_BASE,
109 		       CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
110 	register_serial_console(&console_data.chip);
111 }
112