1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016, Xilinx Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <platform_config.h> 30 31 #include <stdint.h> 32 #include <string.h> 33 34 #include <drivers/gic.h> 35 #include <drivers/cdns_uart.h> 36 #include <drivers/zynqmp_csu.h> 37 38 #include <arm.h> 39 #include <console.h> 40 #include <io.h> 41 #include <kernel/boot.h> 42 #include <kernel/misc.h> 43 #include <kernel/tee_common_otp.h> 44 #include <kernel/tee_time.h> 45 #include <mm/core_memprot.h> 46 #include <tee/tee_fs.h> 47 #include <trace.h> 48 49 static struct cdns_uart_data console_data __nex_bss; 50 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 52 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE), 53 CORE_MMU_PGDIR_SIZE); 54 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 56 ROUNDDOWN(GIC_BASE, CORE_MMU_PGDIR_SIZE), 57 CORE_MMU_PGDIR_SIZE); 58 59 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 60 ROUNDDOWN(GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE), 61 CORE_MMU_PGDIR_SIZE); 62 #if defined(CFG_ZYNQMP_CSU) 63 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CSU_BASE, CSU_SIZE); 64 #endif 65 66 #if CFG_DDR_SIZE > 0x80000000 67 68 #ifdef CFG_ARM32_core 69 #error DDR size over 2 GiB is not supported in 32 bit ARM mode 70 #endif 71 72 register_ddr(DRAM0_BASE, 0x80000000); 73 register_ddr(DRAM1_BASE, CFG_DDR_SIZE - 0x80000000); 74 #else 75 register_ddr(DRAM0_BASE, CFG_DDR_SIZE); 76 #endif 77 78 void main_init_gic(void) 79 { 80 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 81 gic_init_base_addr(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 82 } 83 84 void console_init(void) 85 { 86 cdns_uart_init(&console_data, CONSOLE_UART_BASE, 87 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 88 register_serial_console(&console_data.chip); 89 } 90 91 #if defined(CFG_RPMB_FS) 92 bool plat_rpmb_key_is_ready(void) 93 { 94 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); 95 struct tee_hw_unique_key hwkey = { }; 96 uint32_t status = 0; 97 98 if (tee_otp_get_hw_unique_key(&hwkey)) 99 return false; 100 101 /* 102 * For security reasons, we don't allow writing the RPMB key using the 103 * development HUK even though it is unique. 104 */ 105 status = io_read32(csu + ZYNQMP_CSU_STATUS_OFFSET); 106 if (status & ZYNQMP_CSU_STATUS_AUTH) 107 return true; 108 109 return false; 110 } 111 #endif 112