1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2019 Broadcom. 4 */ 5 6 #include <console.h> 7 #include <drivers/gic.h> 8 #include <drivers/serial8250_uart.h> 9 #include <kernel/generic_boot.h> 10 #include <kernel/panic.h> 11 #include <kernel/pm_stubs.h> 12 #include <mm/core_memprot.h> 13 #include <mm/tee_pager.h> 14 #include <platform_config.h> 15 #include <stdint.h> 16 #include <tee/entry_fast.h> 17 #include <tee/entry_std.h> 18 19 static void secure_intr_handler(void); 20 21 static const struct thread_handlers handlers = { 22 .fast_smc = tee_entry_fast, 23 .nintr = secure_intr_handler, 24 .cpu_on = cpu_on_handler, 25 .cpu_off = pm_do_nothing, 26 .cpu_suspend = pm_do_nothing, 27 .cpu_resume = pm_do_nothing, 28 .system_off = pm_do_nothing, 29 .system_reset = pm_do_nothing, 30 }; 31 32 static struct gic_data gic_data; 33 struct serial8250_uart_data console_data; 34 35 #ifdef BCM_DEVICE0_BASE 36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE0_BASE, BCM_DEVICE0_SIZE); 37 #endif 38 #ifdef BCM_DEVICE1_BASE 39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE1_BASE, BCM_DEVICE1_SIZE); 40 #endif 41 #ifdef BCM_DEVICE2_BASE 42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE2_BASE, BCM_DEVICE2_SIZE); 43 #endif 44 #ifdef BCM_DEVICE3_BASE 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE3_BASE, BCM_DEVICE3_SIZE); 46 #endif 47 #ifdef BCM_DRAM0_NS_BASE 48 register_dynamic_shm(BCM_DRAM0_NS_BASE, BCM_DRAM0_NS_SIZE); 49 #endif 50 #ifdef BCM_DRAM1_NS_BASE 51 register_dynamic_shm(BCM_DRAM1_NS_BASE, BCM_DRAM1_NS_SIZE); 52 #endif 53 #ifdef BCM_DRAM2_NS_BASE 54 register_dynamic_shm(BCM_DRAM2_NS_BASE, BCM_DRAM2_NS_SIZE); 55 #endif 56 57 const struct thread_handlers *generic_boot_get_handlers(void) 58 { 59 return &handlers; 60 } 61 62 void console_init(void) 63 { 64 serial8250_uart_init(&console_data, CONSOLE_UART_BASE, 65 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 66 register_serial_console(&console_data.chip); 67 } 68 69 static void secure_intr_handler(void) 70 { 71 gic_it_handle(&gic_data); 72 } 73 74 void main_init_gic(void) 75 { 76 vaddr_t gicd_base; 77 78 gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC); 79 80 if (!gicd_base) 81 panic(); 82 83 gic_init_base_addr(&gic_data, 0, gicd_base); 84 itr_init(&gic_data.chip); 85 86 } 87