1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 4 */ 5 6#include <arm32.h> 7#include <arm32_macros.S> 8#include <arm32_macros_cortex_a9.S> 9#include <asm.S> 10#include <kernel/tz_ssvce_def.h> 11#include <platform_config.h> 12 13.section .text 14.balign 4 15.code 32 16 17/* 18 * void arm_cl2_enable(vaddr_t pl310_base) - Memory Cache Level2 Enable Function 19 * 20 * If PL310 supports FZLW, enable also FZL in A9 core 21 * 22 * Use scratables registers R0-R3. 23 * No stack usage. 24 * LR store return address. 25 * Trap CPU in case of error. 26 * TODO: to be moved to PL310 code (tz_svce_pl310.S ?) 27 */ 28FUNC arm_cl2_enable , : 29UNWIND( .fnstart) 30 31 /* Enable PL310 ctrl -> only set lsb bit */ 32 mov r1, #0x1 33 str r1, [r0, #PL310_CTRL] 34 35 /* if L2 FLZW enable, enable in L1 */ 36 ldr r1, [r0, #PL310_AUX_CTRL] 37 tst r1, #(1 << 0) /* test AUX_CTRL[FLZ] */ 38 read_actlr r0 39 orrne r0, r0, #(1 << 3) /* enable ACTLR[FLZW] */ 40 write_actlr r0 41 42 mov pc, lr 43 44UNWIND( .fnend) 45END_FUNC arm_cl2_enable 46 47/* 48 * Cortex A9 configuration early configuration 49 * 50 * Use scratables registers R0-R3. 51 * No stack usage. 52 * LR store return address. 53 * Trap CPU in case of error. 54 */ 55FUNC plat_cpu_reset_early , : 56UNWIND( .fnstart) 57 58 /* CPSR.A can be modified in any security state. */ 59 mov_imm r0, SCR_AW 60 write_scr r0 61 62 mov_imm r0, CPU_SCTLR_INIT 63 write_sctlr r0 64 65 mov_imm r0, CPU_ACTLR_INIT 66 write_actlr r0 67 68 mov_imm r0, CPU_NSACR_INIT 69 write_nsacr r0 70 71 mov_imm r0, CPU_PCR_INIT 72 write_pcr r0 73 74 mov pc, lr 75 76UNWIND( .fnend) 77END_FUNC plat_cpu_reset_early 78 79