1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * Copyright 2019 NXP 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm.h> 32 #include <console.h> 33 #include <drivers/gic.h> 34 #include <drivers/imx_uart.h> 35 #include <io.h> 36 #include <imx.h> 37 #include <kernel/generic_boot.h> 38 #include <kernel/misc.h> 39 #include <kernel/panic.h> 40 #include <kernel/pm_stubs.h> 41 #include <mm/core_mmu.h> 42 #include <mm/core_memprot.h> 43 #include <platform_config.h> 44 #include <stdint.h> 45 #include <sm/optee_smc.h> 46 #include <tee/entry_fast.h> 47 #include <tee/entry_std.h> 48 49 50 static void main_fiq(void); 51 static struct gic_data gic_data; 52 53 static const struct thread_handlers handlers = { 54 .nintr = main_fiq, 55 #if defined(CFG_WITH_ARM_TRUSTED_FW) 56 .cpu_on = cpu_on_handler, 57 .cpu_off = pm_do_nothing, 58 .cpu_suspend = pm_do_nothing, 59 .cpu_resume = pm_do_nothing, 60 .system_off = pm_do_nothing, 61 .system_reset = pm_do_nothing, 62 #else 63 .cpu_on = pm_panic, 64 .cpu_off = pm_panic, 65 .cpu_suspend = pm_panic, 66 .cpu_resume = pm_panic, 67 .system_off = pm_panic, 68 .system_reset = pm_panic, 69 #endif 70 }; 71 72 static struct imx_uart_data console_data; 73 74 #ifdef CONSOLE_UART_BASE 75 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 76 CORE_MMU_PGDIR_SIZE); 77 #endif 78 #ifdef GIC_BASE 79 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 80 #endif 81 #ifdef ANATOP_BASE 82 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_PGDIR_SIZE); 83 #endif 84 #ifdef GICD_BASE 85 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, 0x10000); 86 #endif 87 #ifdef AIPS0_BASE 88 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS0_BASE, 89 ROUNDUP(AIPS0_SIZE, CORE_MMU_PGDIR_SIZE)); 90 #endif 91 #ifdef AIPS1_BASE 92 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS1_BASE, 93 ROUNDUP(AIPS1_SIZE, CORE_MMU_PGDIR_SIZE)); 94 #endif 95 #ifdef AIPS2_BASE 96 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS2_BASE, 97 ROUNDUP(AIPS2_SIZE, CORE_MMU_PGDIR_SIZE)); 98 #endif 99 #ifdef AIPS3_BASE 100 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AIPS3_BASE, 101 ROUNDUP(AIPS3_SIZE, CORE_MMU_PGDIR_SIZE)); 102 #endif 103 #ifdef IRAM_BASE 104 register_phys_mem(MEM_AREA_TEE_COHERENT, 105 ROUNDDOWN(IRAM_BASE, CORE_MMU_PGDIR_SIZE), 106 CORE_MMU_PGDIR_SIZE); 107 #endif 108 #ifdef M4_AIPS_BASE 109 register_phys_mem(MEM_AREA_IO_SEC, M4_AIPS_BASE, M4_AIPS_SIZE); 110 #endif 111 #ifdef IRAM_S_BASE 112 register_phys_mem(MEM_AREA_TEE_COHERENT, 113 ROUNDDOWN(IRAM_S_BASE, CORE_MMU_PGDIR_SIZE), 114 CORE_MMU_PGDIR_SIZE); 115 #endif 116 117 #if defined(CFG_PL310) 118 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 119 ROUNDDOWN(PL310_BASE, CORE_MMU_PGDIR_SIZE), 120 CORE_MMU_PGDIR_SIZE); 121 #endif 122 123 const struct thread_handlers *generic_boot_get_handlers(void) 124 { 125 return &handlers; 126 } 127 128 static void main_fiq(void) 129 { 130 gic_it_handle(&gic_data); 131 } 132 133 void console_init(void) 134 { 135 imx_uart_init(&console_data, CONSOLE_UART_BASE); 136 register_serial_console(&console_data.chip); 137 } 138 139 void main_init_gic(void) 140 { 141 #ifdef CFG_ARM_GICV3 142 vaddr_t gicd_base; 143 144 gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC); 145 146 if (!gicd_base) 147 panic(); 148 149 /* Initialize GIC */ 150 gic_init(&gic_data, 0, gicd_base); 151 itr_init(&gic_data.chip); 152 #else 153 vaddr_t gicc_base; 154 vaddr_t gicd_base; 155 156 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC); 157 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC); 158 159 if (!gicc_base || !gicd_base) 160 panic(); 161 162 /* Initialize GIC */ 163 gic_init(&gic_data, gicc_base, gicd_base); 164 itr_init(&gic_data.chip); 165 #endif 166 } 167 168 #if CFG_TEE_CORE_NB_CORE > 1 169 void main_secondary_init_gic(void) 170 { 171 gic_cpu_init(&gic_data); 172 } 173 #endif 174 175 #if defined(CFG_BOOT_SYNC_CPU) 176 static void psci_boot_allcpus(void) 177 { 178 vaddr_t src_base = core_mmu_get_va(SRC_BASE, MEM_AREA_TEE_COHERENT); 179 uint32_t pa = virt_to_phys((void *)TEE_TEXT_VA_START); 180 181 /* set secondary entry address and release core */ 182 io_write32(src_base + SRC_GPR1 + 8, pa); 183 io_write32(src_base + SRC_GPR1 + 16, pa); 184 io_write32(src_base + SRC_GPR1 + 24, pa); 185 186 io_write32(src_base + SRC_SCR, BM_SRC_SCR_CPU_ENABLE_ALL); 187 } 188 #endif 189 190 void plat_cpu_reset_late(void) 191 { 192 if (!get_core_pos()) { 193 /* primary core */ 194 #if defined(CFG_BOOT_SYNC_CPU) 195 psci_boot_allcpus() 196 #endif 197 imx_configure_tzasc(); 198 } 199 } 200