1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2020, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/hfic.h> 11 #include <drivers/pl011.h> 12 #include <drivers/tzc400.h> 13 #include <initcall.h> 14 #include <keep.h> 15 #include <kernel/boot.h> 16 #include <kernel/interrupt.h> 17 #include <kernel/misc.h> 18 #include <kernel/notif.h> 19 #include <kernel/panic.h> 20 #include <kernel/spinlock.h> 21 #include <kernel/tee_time.h> 22 #include <mm/core_memprot.h> 23 #include <mm/core_mmu.h> 24 #include <platform_config.h> 25 #include <sm/psci.h> 26 #include <stdint.h> 27 #include <string.h> 28 #include <trace.h> 29 30 static struct pl011_data console_data __nex_bss; 31 32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 33 #if defined(PLATFORM_FLAVOR_fvp) 34 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 35 #endif 36 #if defined(PLATFORM_FLAVOR_qemu_virt) 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 38 #endif 39 #ifdef DRAM0_BASE 40 register_ddr(DRAM0_BASE, DRAM0_SIZE); 41 #endif 42 #ifdef DRAM1_BASE 43 register_ddr(DRAM1_BASE, DRAM1_SIZE); 44 #endif 45 46 #ifdef CFG_GIC 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 49 50 void main_init_gic(void) 51 { 52 #if defined(CFG_WITH_ARM_TRUSTED_FW) 53 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 54 gic_init_base_addr(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 55 #else 56 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 57 #endif 58 } 59 60 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 61 void main_secondary_init_gic(void) 62 { 63 gic_cpu_init(); 64 } 65 #endif 66 #endif /*CFG_GIC*/ 67 68 #ifdef CFG_CORE_HAFNIUM_INTC 69 void main_init_gic(void) 70 { 71 hfic_init(); 72 } 73 #endif 74 75 void console_init(void) 76 { 77 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 78 CONSOLE_BAUDRATE); 79 register_serial_console(&console_data.chip); 80 } 81 82 #if (defined(CFG_GIC) || defined(CFG_CORE_HAFNIUM_INTC)) && \ 83 defined(IT_CONSOLE_UART) && \ 84 !defined(CFG_NS_VIRTUALIZATION) && \ 85 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV2)) 86 /* 87 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 88 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 89 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 90 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 91 * will hang in EL3 since the interrupt will just be delivered again and 92 * again. 93 */ 94 95 static void read_console(void) 96 { 97 struct serial_chip *cons = &console_data.chip; 98 99 if (!cons->ops->getchar || !cons->ops->have_rx_data) 100 return; 101 102 while (cons->ops->have_rx_data(cons)) { 103 int ch __maybe_unused = cons->ops->getchar(cons); 104 105 DMSG("got 0x%x", ch); 106 } 107 } 108 109 static enum itr_return console_itr_cb(struct itr_handler *h __maybe_unused) 110 { 111 if (notif_async_is_started()) { 112 /* 113 * Asynchronous notifications are enabled, lets read from 114 * uart in the bottom half instead. 115 */ 116 itr_disable(IT_CONSOLE_UART); 117 notif_send_async(NOTIF_VALUE_DO_BOTTOM_HALF); 118 } else { 119 read_console(); 120 } 121 return ITRR_HANDLED; 122 } 123 124 static struct itr_handler console_itr = { 125 .it = IT_CONSOLE_UART, 126 .flags = ITRF_TRIGGER_LEVEL, 127 .handler = console_itr_cb, 128 }; 129 DECLARE_KEEP_PAGER(console_itr); 130 131 static void atomic_console_notif(struct notif_driver *ndrv __unused, 132 enum notif_event ev __maybe_unused) 133 { 134 DMSG("Asynchronous notifications started, event %d", (int)ev); 135 } 136 DECLARE_KEEP_PAGER(atomic_console_notif); 137 138 static void yielding_console_notif(struct notif_driver *ndrv __unused, 139 enum notif_event ev) 140 { 141 switch (ev) { 142 case NOTIF_EVENT_DO_BOTTOM_HALF: 143 read_console(); 144 itr_enable(IT_CONSOLE_UART); 145 break; 146 case NOTIF_EVENT_STOPPED: 147 DMSG("Asynchronous notifications stopped"); 148 itr_enable(IT_CONSOLE_UART); 149 break; 150 default: 151 EMSG("Unknown event %d", (int)ev); 152 } 153 } 154 155 struct notif_driver console_notif = { 156 .atomic_cb = atomic_console_notif, 157 .yielding_cb = yielding_console_notif, 158 }; 159 160 static TEE_Result init_console_itr(void) 161 { 162 itr_add(&console_itr); 163 itr_enable(IT_CONSOLE_UART); 164 if (IS_ENABLED(CFG_CORE_ASYNC_NOTIF)) 165 notif_register_driver(&console_notif); 166 return TEE_SUCCESS; 167 } 168 driver_init(init_console_itr); 169 #endif 170 171 #ifdef CFG_TZC400 172 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 173 174 static TEE_Result init_tzc400(void) 175 { 176 void *va; 177 178 DMSG("Initializing TZC400"); 179 180 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC, TZC400_REG_SIZE); 181 if (!va) { 182 EMSG("TZC400 not mapped"); 183 panic(); 184 } 185 186 tzc_init((vaddr_t)va); 187 tzc_dump_state(); 188 189 return TEE_SUCCESS; 190 } 191 192 service_init(init_tzc400); 193 #endif /*CFG_TZC400*/ 194 195 #if defined(PLATFORM_FLAVOR_qemu_virt) 196 static void release_secondary_early_hpen(size_t pos) 197 { 198 struct mailbox { 199 uint64_t ep; 200 uint64_t hpen[]; 201 } *mailbox; 202 203 if (cpu_mmu_enabled()) 204 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC, 205 SECRAM_COHERENT_SIZE); 206 else 207 mailbox = (void *)SECRAM_BASE; 208 209 if (!mailbox) 210 panic(); 211 212 mailbox->ep = TEE_LOAD_ADDR; 213 dsb_ishst(); 214 mailbox->hpen[pos] = 1; 215 dsb_ishst(); 216 sev(); 217 } 218 219 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 220 { 221 size_t pos = get_core_pos_mpidr(core_id); 222 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 223 224 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 225 return PSCI_RET_INVALID_PARAMETERS; 226 227 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 228 229 if (core_is_released[pos]) { 230 EMSG("core %zu already released", pos); 231 return PSCI_RET_DENIED; 232 } 233 core_is_released[pos] = true; 234 235 boot_set_core_ns_entry(pos, entry, context_id); 236 release_secondary_early_hpen(pos); 237 238 return PSCI_RET_SUCCESS; 239 } 240 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 241