1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #include <console.h> 7 #include <drivers/pl011.h> 8 #ifdef CFG_SPI 9 #include <drivers/pl022_spi.h> 10 #include <drivers/pl061_gpio.h> 11 #endif 12 #if defined(PLATFORM_FLAVOR_hikey) 13 #include <hikey_peripherals.h> 14 #endif 15 #include <initcall.h> 16 #include <io.h> 17 #include <kernel/generic_boot.h> 18 #include <kernel/panic.h> 19 #include <kernel/pm_stubs.h> 20 #include <mm/tee_pager.h> 21 #include <mm/core_memprot.h> 22 #include <platform_config.h> 23 #include <stdint.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 27 static void main_fiq(void); 28 29 static const struct thread_handlers handlers = { 30 .nintr = main_fiq, 31 .cpu_on = cpu_on_handler, 32 .cpu_off = pm_do_nothing, 33 .cpu_suspend = pm_do_nothing, 34 .cpu_resume = pm_do_nothing, 35 .system_off = pm_do_nothing, 36 .system_reset = pm_do_nothing, 37 }; 38 39 static struct pl011_data console_data; 40 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 42 #if defined(PLATFORM_FLAVOR_hikey) 43 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE); 44 #endif 45 #if defined(CFG_SPI) && defined(PLATFORM_FLAVOR_hikey) 46 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE); 51 #endif 52 register_dynamic_shm(DRAM0_BASE, DRAM0_SIZE_NSEC); 53 #ifdef DRAM1_SIZE_NSEC 54 register_dynamic_shm(DRAM1_BASE, DRAM1_SIZE_NSEC); 55 #endif 56 #ifdef DRAM2_SIZE_NSEC 57 register_dynamic_shm(DRAM2_BASE, DRAM2_SIZE_NSEC); 58 #endif 59 60 const struct thread_handlers *generic_boot_get_handlers(void) 61 { 62 return &handlers; 63 } 64 65 static void main_fiq(void) 66 { 67 panic(); 68 } 69 70 void console_init(void) 71 { 72 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 73 CONSOLE_BAUDRATE); 74 register_serial_console(&console_data.chip); 75 } 76 77 #if defined(PLATFORM_FLAVOR_hikey) 78 #ifdef CFG_SPI 79 void spi_init(void) 80 { 81 uint32_t shifted_val, read_val; 82 vaddr_t peri_base = core_mmu_get_va(PERI_BASE, MEM_AREA_IO_NSEC); 83 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC); 84 vaddr_t pmx1_base = core_mmu_get_va(PMX1_BASE, MEM_AREA_IO_NSEC); 85 86 DMSG("take SPI0 out of reset\n"); 87 shifted_val = PERI_RST3_SSP; 88 /* 89 * no need to read PERI_SC_PERIPH_RSTDIS3 first 90 * as all the bits are processed and cleared after writing 91 */ 92 io_write32(peri_base + PERI_SC_PERIPH_RSTDIS3, shifted_val); 93 DMSG("PERI_SC_PERIPH_RSTDIS3: 0x%x\n", 94 io_read32(peri_base + PERI_SC_PERIPH_RSTDIS3)); 95 96 /* 97 * wait until the requested device is out of reset 98 * and ready to be used 99 */ 100 do { 101 read_val = io_read32(peri_base + PERI_SC_PERIPH_RSTSTAT3); 102 } while (read_val & shifted_val); 103 DMSG("PERI_SC_PERIPH_RSTSTAT3: 0x%x\n", read_val); 104 105 DMSG("enable SPI clock\n"); 106 /* 107 * no need to read PERI_SC_PERIPH_CLKEN3 first 108 * as all the bits are processed and cleared after writing 109 */ 110 shifted_val = PERI_CLK3_SSP; 111 io_write32(peri_base + PERI_SC_PERIPH_CLKEN3, shifted_val); 112 DMSG("PERI_SC_PERIPH_CLKEN3: 0x%x\n", 113 io_read32(peri_base + PERI_SC_PERIPH_CLKEN3)); 114 115 DMSG("PERI_SC_PERIPH_CLKSTAT3: 0x%x\n", 116 io_read32(peri_base + PERI_SC_PERIPH_CLKSTAT3)); 117 118 /* 119 * GPIO6_2 can be configured as PINMUX_GPIO, but as PINMUX_SPI, HW IP 120 * will control the chip select pin so we don't have to manually do it. 121 * The only concern is that the IP will pulse it between each packet, 122 * which might not work with certain clients. There seems to be no 123 * option to configure it to stay enabled for the total duration of the 124 * transfer. 125 * ref: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/CJACFAFG.html 126 */ 127 DMSG("configure gpio6 pins 0-3 as SPI\n"); 128 io_write32(pmx0_base + PMX0_IOMG104, PINMUX_SPI); 129 io_write32(pmx0_base + PMX0_IOMG105, PINMUX_SPI); 130 io_write32(pmx0_base + PMX0_IOMG106, PINMUX_SPI); 131 io_write32(pmx0_base + PMX0_IOMG107, PINMUX_SPI); 132 133 DMSG("configure gpio6 pins 0-3 as nopull\n"); 134 io_write32(pmx1_base + PMX1_IOCG104, PINCFG_NOPULL); 135 io_write32(pmx1_base + PMX1_IOCG105, PINCFG_NOPULL); 136 io_write32(pmx1_base + PMX1_IOCG106, PINCFG_NOPULL); 137 io_write32(pmx1_base + PMX1_IOCG107, PINCFG_NOPULL); 138 139 #ifdef CFG_SPI_TEST 140 spi_test(); 141 #endif 142 } 143 #endif 144 145 static TEE_Result peripherals_init(void) 146 { 147 vaddr_t pmussi_base = core_mmu_get_va(PMUSSI_BASE, MEM_AREA_IO_NSEC); 148 149 DMSG("enable LD021_1V8 source (pin 35) on LS connector\n"); 150 /* 151 * Mezzanine cards usually use this to source level shifters for 152 * UART, GPIO, SPI, I2C, etc so if not enabled, connected 153 * peripherals will not work either (during bootloader stage) 154 * until linux is booted. 155 */ 156 io_mask8(pmussi_base + PMUSSI_LDO21_REG_ADJ, PMUSSI_LDO21_REG_VL_1V8, 157 PMUSSI_LDO21_REG_VL_MASK); 158 io_write8(pmussi_base + PMUSSI_ENA_LDO17_22, PMUSSI_ENA_LDO21); 159 160 #ifdef CFG_SPI 161 spi_init(); 162 #endif 163 return TEE_SUCCESS; 164 } 165 166 driver_init(peripherals_init); 167 #endif /* PLATFORM_FLAVOR_hikey */ 168