1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright (c) 2016, Wind River Systems. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm32.h> 32 #include <console.h> 33 #include <drivers/cdns_uart.h> 34 #include <drivers/gic.h> 35 #include <io.h> 36 #include <kernel/generic_boot.h> 37 #include <kernel/misc.h> 38 #include <kernel/panic.h> 39 #include <kernel/pm_stubs.h> 40 #include <kernel/tz_ssvce_pl310.h> 41 #include <mm/core_mmu.h> 42 #include <mm/core_memprot.h> 43 #include <platform_config.h> 44 #include <platform_smc.h> 45 #include <stdint.h> 46 #include <tee/entry_fast.h> 47 #include <tee/entry_std.h> 48 49 static void main_fiq(void); 50 static void platform_tee_entry_fast(struct thread_smc_args *args); 51 52 static const struct thread_handlers handlers = { 53 .fast_smc = platform_tee_entry_fast, 54 .nintr = main_fiq, 55 .cpu_on = pm_panic, 56 .cpu_off = pm_panic, 57 .cpu_suspend = pm_panic, 58 .cpu_resume = pm_panic, 59 .system_off = pm_panic, 60 .system_reset = pm_panic, 61 }; 62 63 static struct gic_data gic_data; 64 static struct cdns_uart_data console_data; 65 66 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 67 CORE_MMU_PGDIR_SIZE); 68 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 69 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE); 70 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE); 71 72 const struct thread_handlers *generic_boot_get_handlers(void) 73 { 74 return &handlers; 75 } 76 77 static void main_fiq(void) 78 { 79 panic(); 80 } 81 82 void plat_cpu_reset_late(void) 83 { 84 if (!get_core_pos()) { 85 /* primary core */ 86 #if defined(CFG_BOOT_SECONDARY_REQUEST) 87 /* set secondary entry address and release core */ 88 io_write32(SECONDARY_ENTRY_DROP, TEE_LOAD_ADDR); 89 dsb(); 90 sev(); 91 #endif 92 93 /* SCU config */ 94 io_write32(SCU_BASE + SCU_INV_SEC, SCU_INV_CTRL_INIT); 95 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_CTRL_INIT); 96 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_CTRL_INIT); 97 98 /* SCU enable */ 99 io_setbits32(SCU_BASE + SCU_CTRL, 0x1); 100 101 /* NS Access control */ 102 io_write32(SECURITY2_SDIO0, ACCESS_BITS_ALL); 103 io_write32(SECURITY3_SDIO1, ACCESS_BITS_ALL); 104 io_write32(SECURITY4_QSPI, ACCESS_BITS_ALL); 105 io_write32(SECURITY6_APB_SLAVES, ACCESS_BITS_ALL); 106 107 io_write32(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK); 108 109 io_write32(SLCR_TZ_DDR_RAM, ACCESS_BITS_ALL); 110 io_write32(SLCR_TZ_DMA_NS, ACCESS_BITS_ALL); 111 io_write32(SLCR_TZ_DMA_IRQ_NS, ACCESS_BITS_ALL); 112 io_write32(SLCR_TZ_DMA_PERIPH_NS, ACCESS_BITS_ALL); 113 io_write32(SLCR_TZ_GEM, ACCESS_BITS_ALL); 114 io_write32(SLCR_TZ_SDIO, ACCESS_BITS_ALL); 115 io_write32(SLCR_TZ_USB, ACCESS_BITS_ALL); 116 117 io_write32(SLCR_LOCK, SLCR_LOCK_MAGIC); 118 } 119 } 120 121 void console_init(void) 122 { 123 cdns_uart_init(&console_data, CONSOLE_UART_BASE, 0, 0); 124 register_serial_console(&console_data.chip); 125 } 126 127 vaddr_t pl310_base(void) 128 { 129 static void *va; 130 131 if (cpu_mmu_enabled()) { 132 if (!va) 133 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 134 return (vaddr_t)va; 135 } 136 return PL310_BASE; 137 } 138 139 void arm_cl2_config(vaddr_t pl310_base) 140 { 141 /* Disable PL310 */ 142 io_write32(pl310_base + PL310_CTRL, 0); 143 144 /* 145 * Xilinx AR#54190 recommends setting L2C RAM in SLCR 146 * to 0x00020202 for proper cache operations. 147 */ 148 io_write32(SLCR_L2C_RAM, SLCR_L2C_RAM_VALUE); 149 150 io_write32(pl310_base + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); 151 io_write32(pl310_base + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); 152 io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); 153 io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); 154 io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); 155 156 /* invalidate all cache ways */ 157 arm_cl2_invbyway(pl310_base); 158 } 159 160 void arm_cl2_enable(vaddr_t pl310_base) 161 { 162 uint32_t val; 163 164 /* Enable PL310 ctrl -> only set lsb bit */ 165 io_write32(pl310_base + PL310_CTRL, 1); 166 167 /* if L2 FLZW enable, enable in L1 */ 168 val = io_read32(pl310_base + PL310_AUX_CTRL); 169 if (val & 1) 170 write_actlr(read_actlr() | (1 << 3)); 171 } 172 173 void main_init_gic(void) 174 { 175 vaddr_t gicc_base; 176 vaddr_t gicd_base; 177 178 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 179 MEM_AREA_IO_SEC); 180 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 181 MEM_AREA_IO_SEC); 182 183 if (!gicc_base || !gicd_base) 184 panic(); 185 186 /* Initialize GIC */ 187 gic_init(&gic_data, gicc_base, gicd_base); 188 itr_init(&gic_data.chip); 189 } 190 191 void main_secondary_init_gic(void) 192 { 193 gic_cpu_init(&gic_data); 194 } 195 196 static vaddr_t slcr_access_range[] = { 197 0x004, 0x008, /* lock, unlock */ 198 0x100, 0x1FF, /* PLL */ 199 0x200, 0x2FF, /* Reset */ 200 0xA00, 0xAFF /* L2C */ 201 }; 202 203 static uint32_t write_slcr(uint32_t addr, uint32_t val) 204 { 205 uint32_t i; 206 207 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 208 if (addr >= slcr_access_range[i] && 209 addr <= slcr_access_range[i+1]) { 210 static vaddr_t va; 211 212 if (!va) 213 va = (vaddr_t)phys_to_virt(SLCR_BASE, 214 MEM_AREA_IO_SEC); 215 io_write32(va + addr, val); 216 return OPTEE_SMC_RETURN_OK; 217 } 218 } 219 return OPTEE_SMC_RETURN_EBADADDR; 220 } 221 222 static uint32_t read_slcr(uint32_t addr, uint32_t *val) 223 { 224 uint32_t i; 225 226 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 227 if (addr >= slcr_access_range[i] && 228 addr <= slcr_access_range[i+1]) { 229 static vaddr_t va; 230 231 if (!va) 232 va = (vaddr_t)phys_to_virt(SLCR_BASE, 233 MEM_AREA_IO_SEC); 234 *val = io_read32(va + addr); 235 return OPTEE_SMC_RETURN_OK; 236 } 237 } 238 return OPTEE_SMC_RETURN_EBADADDR; 239 } 240 241 static void platform_tee_entry_fast(struct thread_smc_args *args) 242 { 243 switch (args->a0) { 244 case ZYNQ7K_SMC_SLCR_WRITE: 245 args->a0 = write_slcr(args->a1, args->a2); 246 break; 247 case ZYNQ7K_SMC_SLCR_READ: 248 args->a0 = read_slcr(args->a1, &args->a2); 249 break; 250 default: 251 tee_entry_fast(args); 252 break; 253 } 254 } 255