1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/pl011.h> 11 #include <drivers/tzc400.h> 12 #include <initcall.h> 13 #include <keep.h> 14 #include <kernel/generic_boot.h> 15 #include <kernel/misc.h> 16 #include <kernel/panic.h> 17 #include <kernel/pm_stubs.h> 18 #include <kernel/tee_time.h> 19 #include <mm/core_memprot.h> 20 #include <mm/core_mmu.h> 21 #include <platform_config.h> 22 #include <sm/psci.h> 23 #include <stdint.h> 24 #include <string.h> 25 #include <tee/entry_fast.h> 26 #include <tee/entry_std.h> 27 #include <trace.h> 28 29 static void main_fiq(void); 30 31 static const struct thread_handlers handlers = { 32 .fast_smc = tee_entry_fast, 33 .nintr = main_fiq, 34 #if defined(CFG_WITH_ARM_TRUSTED_FW) 35 .cpu_on = cpu_on_handler, 36 .cpu_off = pm_do_nothing, 37 .cpu_suspend = pm_do_nothing, 38 .cpu_resume = pm_do_nothing, 39 .system_off = pm_do_nothing, 40 .system_reset = pm_do_nothing, 41 #else 42 .cpu_on = pm_panic, 43 .cpu_off = pm_panic, 44 .cpu_suspend = pm_panic, 45 .cpu_resume = pm_panic, 46 .system_off = pm_panic, 47 .system_reset = pm_panic, 48 #endif 49 }; 50 51 static struct gic_data gic_data __nex_bss; 52 static struct pl011_data console_data __nex_bss; 53 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 55 #if defined(PLATFORM_FLAVOR_fvp) 56 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 57 #endif 58 #if defined(PLATFORM_FLAVOR_qemu_virt) 59 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 60 #endif 61 #ifdef DRAM0_BASE 62 register_ddr(DRAM0_BASE, DRAM0_SIZE); 63 #endif 64 #ifdef DRAM1_BASE 65 register_ddr(DRAM1_BASE, DRAM1_SIZE); 66 #endif 67 68 const struct thread_handlers *generic_boot_get_handlers(void) 69 { 70 return &handlers; 71 } 72 73 #ifdef GIC_BASE 74 75 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 76 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 77 78 void main_init_gic(void) 79 { 80 vaddr_t gicc_base; 81 vaddr_t gicd_base; 82 83 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 84 MEM_AREA_IO_SEC); 85 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 86 MEM_AREA_IO_SEC); 87 if (!gicc_base || !gicd_base) 88 panic(); 89 90 #if defined(CFG_WITH_ARM_TRUSTED_FW) 91 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 92 gic_init_base_addr(&gic_data, gicc_base, gicd_base); 93 #else 94 /* Initialize GIC */ 95 gic_init(&gic_data, gicc_base, gicd_base); 96 #endif 97 itr_init(&gic_data.chip); 98 } 99 100 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 101 void main_secondary_init_gic(void) 102 { 103 gic_cpu_init(&gic_data); 104 } 105 #endif 106 107 #endif 108 109 static void main_fiq(void) 110 { 111 gic_it_handle(&gic_data); 112 } 113 114 void console_init(void) 115 { 116 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 117 CONSOLE_BAUDRATE); 118 register_serial_console(&console_data.chip); 119 } 120 121 #if defined(IT_CONSOLE_UART) && \ 122 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV3)) 123 /* 124 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 125 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 126 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 127 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 128 * will hang in EL3 since the interrupt will just be delivered again and 129 * again. 130 */ 131 static enum itr_return console_itr_cb(struct itr_handler *h __unused) 132 { 133 struct serial_chip *cons = &console_data.chip; 134 135 while (cons->ops->have_rx_data(cons)) { 136 int ch __maybe_unused = cons->ops->getchar(cons); 137 138 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); 139 } 140 return ITRR_HANDLED; 141 } 142 143 static struct itr_handler console_itr = { 144 .it = IT_CONSOLE_UART, 145 .flags = ITRF_TRIGGER_LEVEL, 146 .handler = console_itr_cb, 147 }; 148 KEEP_PAGER(console_itr); 149 150 static TEE_Result init_console_itr(void) 151 { 152 itr_add(&console_itr); 153 itr_enable(IT_CONSOLE_UART); 154 return TEE_SUCCESS; 155 } 156 driver_init(init_console_itr); 157 #endif 158 159 #ifdef CFG_TZC400 160 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 161 162 static TEE_Result init_tzc400(void) 163 { 164 void *va; 165 166 DMSG("Initializing TZC400"); 167 168 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC); 169 if (!va) { 170 EMSG("TZC400 not mapped"); 171 panic(); 172 } 173 174 tzc_init((vaddr_t)va); 175 tzc_dump_state(); 176 177 return TEE_SUCCESS; 178 } 179 180 service_init(init_tzc400); 181 #endif /*CFG_TZC400*/ 182 183 #if defined(PLATFORM_FLAVOR_qemu_virt) 184 static void release_secondary_early_hpen(size_t pos) 185 { 186 struct mailbox { 187 uint64_t ep; 188 uint64_t hpen[]; 189 } *mailbox; 190 191 if (cpu_mmu_enabled()) 192 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC); 193 else 194 mailbox = (void *)SECRAM_BASE; 195 196 if (!mailbox) 197 panic(); 198 199 mailbox->ep = TEE_LOAD_ADDR; 200 dsb_ishst(); 201 mailbox->hpen[pos] = 1; 202 dsb_ishst(); 203 sev(); 204 } 205 206 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 207 { 208 size_t pos = get_core_pos_mpidr(core_id); 209 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 210 211 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 212 return PSCI_RET_INVALID_PARAMETERS; 213 214 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 215 216 if (core_is_released[pos]) { 217 EMSG("core %zu already released", pos); 218 return PSCI_RET_DENIED; 219 } 220 core_is_released[pos] = true; 221 222 generic_boot_set_core_ns_entry(pos, entry, context_id); 223 release_secondary_early_hpen(pos); 224 225 return PSCI_RET_SUCCESS; 226 } 227 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 228