1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 4 */ 5 6 #include <arm32.h> 7 #include <console.h> 8 #include <drivers/gic.h> 9 #include <drivers/stih_asc.h> 10 #include <io.h> 11 #include <kernel/generic_boot.h> 12 #include <kernel/misc.h> 13 #include <kernel/panic.h> 14 #include <kernel/pm_stubs.h> 15 #include <kernel/tz_ssvce_pl310.h> 16 #include <mm/core_mmu.h> 17 #include <mm/core_memprot.h> 18 #include <platform_config.h> 19 #include <stdint.h> 20 #include <tee/entry_std.h> 21 #include <tee/entry_fast.h> 22 #include <trace.h> 23 #include <util.h> 24 25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CPU_IOMEM_BASE, CPU_IOMEM_SIZE); 26 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG_BASE, RNG_SIZE); 27 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, STIH_ASC_REG_SIZE); 28 29 #ifdef DRAM0_BASE 30 register_ddr(DRAM0_BASE, DRAM0_SIZE); 31 #endif 32 #ifdef DRAM1_BASE 33 register_ddr(DRAM1_BASE, DRAM1_SIZE); 34 #endif 35 36 static struct gic_data gic_data; 37 static struct stih_asc_pd console_data; 38 39 static void main_fiq(void); 40 41 #if defined(PLATFORM_FLAVOR_b2260) 42 static bool ns_resources_ready(void) 43 { 44 return true; 45 } 46 #else 47 /* some nonsecure resource might not be ready (uart) */ 48 static int boot_is_completed; 49 static bool ns_resources_ready(void) 50 { 51 return !!boot_is_completed; 52 } 53 54 /* Overriding the default __weak tee_entry_std() */ 55 uint32_t tee_entry_std(struct optee_msg_arg *arg, uint32_t num_params) 56 { 57 boot_is_completed = 1; 58 59 return __tee_entry_std(arg, num_params); 60 } 61 #endif 62 63 static const struct thread_handlers handlers = { 64 .fast_smc = tee_entry_fast, 65 .nintr = main_fiq, 66 .cpu_on = pm_panic, 67 .cpu_off = pm_panic, 68 .cpu_suspend = pm_panic, 69 .cpu_resume = pm_panic, 70 .system_off = pm_panic, 71 .system_reset = pm_panic, 72 }; 73 74 const struct thread_handlers *generic_boot_get_handlers(void) 75 { 76 return &handlers; 77 } 78 79 void console_init(void) 80 { 81 stih_asc_init(&console_data, UART_CONSOLE_BASE); 82 } 83 84 void console_putc(int ch) 85 { 86 87 if (ns_resources_ready()) { 88 struct serial_chip *cons = &console_data.chip; 89 90 if (ch == '\n') 91 cons->ops->putc(cons, '\r'); 92 cons->ops->putc(cons, ch); 93 } 94 } 95 96 void console_flush(void) 97 { 98 if (ns_resources_ready()) { 99 struct serial_chip *cons = &console_data.chip; 100 101 cons->ops->flush(cons); 102 } 103 } 104 105 vaddr_t pl310_base(void) 106 { 107 static void *va; 108 109 if (cpu_mmu_enabled()) { 110 if (!va) 111 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 112 return (vaddr_t)va; 113 } 114 return PL310_BASE; 115 } 116 117 void arm_cl2_config(vaddr_t pl310) 118 { 119 /* pl310 off */ 120 io_write32(pl310 + PL310_CTRL, 0); 121 122 /* config PL310 */ 123 io_write32(pl310 + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); 124 io_write32(pl310 + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); 125 io_write32(pl310 + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); 126 io_write32(pl310 + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); 127 io_write32(pl310 + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); 128 129 /* invalidate all pl310 cache ways */ 130 arm_cl2_invbyway(pl310); 131 } 132 133 void plat_cpu_reset_late(void) 134 { 135 int i; 136 137 assert(!cpu_mmu_enabled()); 138 139 /* Allow NSec to Imprecise abort */ 140 write_scr(SCR_AW); 141 142 if (get_core_pos()) 143 return; 144 145 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_INIT); 146 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_INIT); 147 io_write32(SCU_BASE + SCU_FILT_EA, CPU_PORT_FILT_END); 148 io_write32(SCU_BASE + SCU_FILT_SA, CPU_PORT_FILT_START); 149 io_write32(SCU_BASE + SCU_CTRL, SCU_CTRL_INIT); 150 151 io_write32(pl310_base() + PL310_ADDR_FILT_END, CPU_PORT_FILT_END); 152 io_write32(pl310_base() + PL310_ADDR_FILT_START, 153 CPU_PORT_FILT_START | PL310_CTRL_ENABLE_BIT); 154 155 /* TODO: gic_init scan fails, pre-init all SPIs are nonsecure */ 156 for (i = 0; i < (31 * 4); i += 4) 157 io_write32(GIC_DIST_BASE + GIC_DIST_ISR1 + i, 0xFFFFFFFF); 158 } 159 160 void main_init_gic(void) 161 { 162 vaddr_t gicc_base; 163 vaddr_t gicd_base; 164 165 gicc_base = (vaddr_t)phys_to_virt(GIC_CPU_BASE, MEM_AREA_IO_SEC); 166 gicd_base = (vaddr_t)phys_to_virt(GIC_DIST_BASE, MEM_AREA_IO_SEC); 167 168 if (!gicc_base || !gicd_base) 169 panic(); 170 171 gic_init(&gic_data, gicc_base, gicd_base); 172 itr_init(&gic_data.chip); 173 } 174 175 void main_secondary_init_gic(void) 176 { 177 gic_cpu_init(&gic_data); 178 } 179 180 static void main_fiq(void) 181 { 182 gic_it_handle(&gic_data); 183 } 184