1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) Foundries Ltd. 2022 - All Rights Reserved 4 */ 5 6 #include <arm.h> 7 #include <assert.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/pl011.h> 11 #include <drivers/versal_pm.h> 12 #include <io.h> 13 #include <kernel/boot.h> 14 #include <kernel/misc.h> 15 #include <kernel/tee_time.h> 16 #include <mm/core_memprot.h> 17 #include <platform_config.h> 18 #include <stdint.h> 19 #include <string.h> 20 #include <tee/tee_fs.h> 21 #include <trace.h> 22 23 #define VERSAL_AHWROT_SECURED 0xA5A5A5A5 24 #define VERSAL_SHWROT_SECURED 0x96969696 25 #define VERSAL_AHWROT_REG 0x14C 26 #define VERSAL_SHWROT_REG 0x150 27 28 static struct pl011_data console_data; 29 30 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 31 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE), 32 CORE_MMU_PGDIR_SIZE); 33 34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 35 GIC_BASE, CORE_MMU_PGDIR_SIZE); 36 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 38 GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE); 39 40 register_phys_mem(MEM_AREA_IO_SEC, PLM_RTCA, PLM_RTCA_LEN); 41 42 register_ddr(DRAM0_BASE, DRAM0_SIZE); 43 44 #if defined(DRAM1_BASE) 45 register_ddr(DRAM1_BASE, DRAM1_SIZE); 46 register_ddr(DRAM2_BASE, DRAM2_SIZE); 47 #endif 48 49 void main_init_gic(void) 50 { 51 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 52 gic_init_base_addr(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 53 } 54 55 void console_init(void) 56 { 57 pl011_init(&console_data, CONSOLE_UART_BASE, 58 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 59 register_serial_console(&console_data.chip); 60 } 61 62 static TEE_Result platform_banner(void) 63 { 64 vaddr_t plm_rtca = (vaddr_t)phys_to_virt(PLM_RTCA, MEM_AREA_IO_SEC, 65 PLM_RTCA_LEN); 66 const char *ahwrot_str = "OFF"; 67 const char *shwrot_str = "OFF"; 68 uint8_t version = 0; 69 70 assert(plm_rtca); 71 72 if (versal_soc_version(&version)) { 73 EMSG("Failure to retrieve SoC version"); 74 return TEE_ERROR_GENERIC; 75 } 76 77 IMSG("Platform Versal:\tSilicon Revision v%"PRIu8, version); 78 79 if (io_read32(plm_rtca + VERSAL_AHWROT_REG) == VERSAL_AHWROT_SECURED) 80 ahwrot_str = "ON"; 81 82 if (io_read32(plm_rtca + VERSAL_SHWROT_REG) == VERSAL_SHWROT_SECURED) 83 shwrot_str = "ON"; 84 85 IMSG("Hardware Root of Trust: Asymmetric[%s], Symmetric[%s]", 86 ahwrot_str, shwrot_str); 87 88 return TEE_SUCCESS; 89 } 90 91 #if defined(CFG_RPMB_FS) 92 bool plat_rpmb_key_is_ready(void) 93 { 94 vaddr_t plm_rtca = (vaddr_t)phys_to_virt(PLM_RTCA, MEM_AREA_IO_SEC, 95 PLM_RTCA_LEN); 96 97 assert(plm_rtca); 98 99 if (io_read32(plm_rtca + VERSAL_AHWROT_REG) == VERSAL_AHWROT_SECURED) 100 return true; 101 102 if (io_read32(plm_rtca + VERSAL_SHWROT_REG) == VERSAL_SHWROT_SECURED) 103 return true; 104 105 return false; 106 } 107 #endif 108 109 service_init(platform_banner); 110 111 #if defined(CFG_VERSAL_FPGA_DDR_ADDR) 112 static TEE_Result program_fpga(void) 113 { 114 return versal_write_fpga(CFG_VERSAL_FPGA_DDR_ADDR); 115 } 116 117 service_init(program_fpga); 118 #endif 119