1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #include <platform_config.h> 7 #include <console.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <assert.h> 11 #include <drivers/gic.h> 12 #include <drivers/serial8250_uart.h> 13 #include <arm.h> 14 #include <kernel/generic_boot.h> 15 #include <kernel/panic.h> 16 #include <kernel/pm_stubs.h> 17 #include <trace.h> 18 #include <kernel/misc.h> 19 #include <kernel/mutex.h> 20 #include <kernel/tee_time.h> 21 #include <kernel/tee_common_otp.h> 22 #include <mm/core_mmu.h> 23 #include <mm/core_memprot.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 #include <console.h> 27 #include <sm/sm.h> 28 29 #define PLAT_HW_UNIQUE_KEY_LENGTH 32 30 31 static struct gic_data gic_data; 32 static struct serial8250_uart_data console_data; 33 static uint8_t plat_huk[PLAT_HW_UNIQUE_KEY_LENGTH]; 34 35 register_phys_mem(MEM_AREA_RAM_SEC, TZDRAM_BASE, TEE_RAM_VA_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 40 SERIAL8250_UART_REG_SIZE); 41 42 void main_init_gic(void) 43 { 44 vaddr_t gicc_base; 45 vaddr_t gicd_base; 46 47 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC); 48 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC); 49 50 if (!gicc_base || !gicd_base) 51 panic(); 52 53 gic_init(&gic_data, gicc_base, gicd_base); 54 itr_init(&gic_data.chip); 55 } 56 57 void main_secondary_init_gic(void) 58 { 59 gic_cpu_init(&gic_data); 60 } 61 62 static void main_fiq(void) 63 { 64 gic_it_handle(&gic_data); 65 } 66 67 static const struct thread_handlers handlers = { 68 .nintr = main_fiq, 69 .cpu_on = pm_panic, 70 .cpu_off = pm_panic, 71 .cpu_suspend = pm_panic, 72 .cpu_resume = pm_panic, 73 .system_off = pm_panic, 74 .system_reset = pm_panic, 75 }; 76 77 const struct thread_handlers *generic_boot_get_handlers(void) 78 { 79 return &handlers; 80 } 81 82 struct plat_nsec_ctx { 83 uint32_t usr_sp; 84 uint32_t usr_lr; 85 uint32_t svc_sp; 86 uint32_t svc_lr; 87 uint32_t svc_spsr; 88 uint32_t abt_sp; 89 uint32_t abt_lr; 90 uint32_t abt_spsr; 91 uint32_t und_sp; 92 uint32_t und_lr; 93 uint32_t und_spsr; 94 uint32_t irq_sp; 95 uint32_t irq_lr; 96 uint32_t irq_spsr; 97 uint32_t fiq_sp; 98 uint32_t fiq_lr; 99 uint32_t fiq_spsr; 100 uint32_t fiq_rx[5]; 101 uint32_t mon_lr; 102 uint32_t mon_spsr; 103 }; 104 105 struct plat_boot_args { 106 struct plat_nsec_ctx nsec_ctx; 107 uint8_t huk[PLAT_HW_UNIQUE_KEY_LENGTH]; 108 }; 109 110 void init_sec_mon(unsigned long nsec_entry) 111 { 112 struct plat_boot_args *plat_boot_args; 113 struct sm_nsec_ctx *nsec_ctx; 114 115 plat_boot_args = phys_to_virt(nsec_entry, MEM_AREA_IO_SEC); 116 if (!plat_boot_args) 117 panic(); 118 119 /* Invalidate cache to fetch data from external memory */ 120 cache_op_inner(DCACHE_AREA_INVALIDATE, 121 plat_boot_args, sizeof(*plat_boot_args)); 122 123 /* Initialize secure monitor */ 124 nsec_ctx = sm_get_nsec_ctx(); 125 126 nsec_ctx->ub_regs.usr_sp = plat_boot_args->nsec_ctx.usr_sp; 127 nsec_ctx->ub_regs.usr_lr = plat_boot_args->nsec_ctx.usr_lr; 128 nsec_ctx->ub_regs.irq_spsr = plat_boot_args->nsec_ctx.irq_spsr; 129 nsec_ctx->ub_regs.irq_sp = plat_boot_args->nsec_ctx.irq_sp; 130 nsec_ctx->ub_regs.irq_lr = plat_boot_args->nsec_ctx.irq_lr; 131 nsec_ctx->ub_regs.svc_spsr = plat_boot_args->nsec_ctx.svc_spsr; 132 nsec_ctx->ub_regs.svc_sp = plat_boot_args->nsec_ctx.svc_sp; 133 nsec_ctx->ub_regs.svc_lr = plat_boot_args->nsec_ctx.svc_lr; 134 nsec_ctx->ub_regs.abt_spsr = plat_boot_args->nsec_ctx.abt_spsr; 135 nsec_ctx->ub_regs.abt_sp = plat_boot_args->nsec_ctx.abt_sp; 136 nsec_ctx->ub_regs.abt_lr = plat_boot_args->nsec_ctx.abt_lr; 137 nsec_ctx->ub_regs.und_spsr = plat_boot_args->nsec_ctx.und_spsr; 138 nsec_ctx->ub_regs.und_sp = plat_boot_args->nsec_ctx.und_sp; 139 nsec_ctx->ub_regs.und_lr = plat_boot_args->nsec_ctx.und_lr; 140 nsec_ctx->mon_lr = plat_boot_args->nsec_ctx.mon_lr; 141 nsec_ctx->mon_spsr = plat_boot_args->nsec_ctx.mon_spsr; 142 143 memcpy(plat_huk, plat_boot_args->huk, sizeof(plat_boot_args->huk)); 144 } 145 146 void console_init(void) 147 { 148 serial8250_uart_init(&console_data, CONSOLE_UART_BASE, 149 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 150 register_serial_console(&console_data.chip); 151 } 152 153 #if defined(CFG_OTP_SUPPORT) 154 155 TEE_Result tee_otp_get_hw_unique_key(struct tee_hw_unique_key *hwkey) 156 { 157 memcpy(&hwkey->data[0], &plat_huk[0], sizeof(hwkey->data)); 158 return TEE_SUCCESS; 159 } 160 161 #endif 162