1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2014, Allwinner Technology Co., Ltd. 4 * Copyright (c) 2018, Linaro Limited 5 * Copyright (c) 2018, Amit Singh Tomar <amittomer25@gmail.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <console.h> 32 #include <io.h> 33 #include <stdint.h> 34 #include <drivers/gic.h> 35 #include <drivers/serial8250_uart.h> 36 #include <drivers/tzc380.h> 37 #include <kernel/generic_boot.h> 38 #include <kernel/misc.h> 39 #include <kernel/panic.h> 40 #include <kernel/pm_stubs.h> 41 #include <kernel/tz_ssvce_def.h> 42 #include <mm/core_mmu.h> 43 #include <mm/core_memprot.h> 44 #include <mm/tee_pager.h> 45 #include <platform_config.h> 46 #include <sm/tee_mon.h> 47 #include <sm/optee_smc.h> 48 #include <tee/entry_fast.h> 49 #include <tee/entry_std.h> 50 51 #ifdef GIC_BASE 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 53 #endif 54 55 #ifdef CONSOLE_UART_BASE 56 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, 57 CONSOLE_UART_BASE, SUNXI_UART_REG_SIZE); 58 #endif 59 60 #ifdef SUNXI_TZPC_BASE 61 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_TZPC_BASE, SUNXI_TZPC_REG_SIZE); 62 #define REG_TZPC_SMTA_DECPORT0_STA_REG (0x0004) 63 #define REG_TZPC_SMTA_DECPORT0_SET_REG (0x0008) 64 #define REG_TZPC_SMTA_DECPORT0_CLR_REG (0x000C) 65 #define REG_TZPC_SMTA_DECPORT1_STA_REG (0x0010) 66 #define REG_TZPC_SMTA_DECPORT1_SET_REG (0x0014) 67 #define REG_TZPC_SMTA_DECPORT1_CLR_REG (0x0018) 68 #define REG_TZPC_SMTA_DECPORT2_STA_REG (0x001c) 69 #define REG_TZPC_SMTA_DECPORT2_SET_REG (0x0020) 70 #define REG_TZPC_SMTA_DECPORT2_CLR_REG (0x0024) 71 #endif 72 73 #ifdef SUNXI_CPUCFG_BASE 74 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_CPUCFG_BASE, 75 SUNXI_CPUCFG_REG_SIZE); 76 #endif 77 78 #ifdef SUNXI_PRCM_BASE 79 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_PRCM_BASE, SUNXI_PRCM_REG_SIZE); 80 #endif 81 82 #ifdef CFG_TZC380 83 vaddr_t smc_base(void); 84 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_SMC_BASE, TZC400_REG_SIZE); 85 #define SMC_MASTER_BYPASS 0x18 86 #define SMC_MASTER_BYPASS_EN_MASK 0x1 87 #endif 88 89 #ifdef GIC_BASE 90 static struct gic_data gic_data; 91 #endif 92 #ifdef SUNXI_TZPC_BASE 93 static void tzpc_init(void); 94 #endif 95 96 static void main_fiq(void) 97 { 98 panic(); 99 } 100 101 static const struct thread_handlers handlers = { 102 .nintr = main_fiq, 103 #if defined(CFG_WITH_ARM_TRUSTED_FW) 104 .cpu_on = cpu_on_handler, 105 .cpu_off = pm_do_nothing, 106 .cpu_suspend = pm_do_nothing, 107 .cpu_resume = pm_do_nothing, 108 .system_off = pm_do_nothing, 109 .system_reset = pm_do_nothing, 110 #else 111 .cpu_on = pm_panic, 112 .cpu_off = pm_panic, 113 .cpu_suspend = pm_panic, 114 .cpu_resume = pm_panic, 115 .system_off = pm_panic, 116 .system_reset = pm_panic, 117 #endif 118 }; 119 120 static struct serial8250_uart_data console_data; 121 122 const struct thread_handlers *generic_boot_get_handlers(void) 123 { 124 return &handlers; 125 } 126 127 void console_init(void) 128 { 129 serial8250_uart_init(&console_data, 130 CONSOLE_UART_BASE, 131 CONSOLE_UART_CLK_IN_HZ, 132 CONSOLE_BAUDRATE); 133 register_serial_console(&console_data.chip); 134 } 135 136 #ifdef SUNXI_TZPC_BASE 137 static void tzpc_init(void) 138 { 139 vaddr_t v = (vaddr_t)phys_to_virt(SUNXI_TZPC_BASE, MEM_AREA_IO_SEC); 140 141 DMSG("SMTA_DECPORT0=%x", io_read32(v + REG_TZPC_SMTA_DECPORT0_STA_REG)); 142 DMSG("SMTA_DECPORT1=%x", io_read32(v + REG_TZPC_SMTA_DECPORT1_STA_REG)); 143 DMSG("SMTA_DECPORT2=%x", io_read32(v + REG_TZPC_SMTA_DECPORT2_STA_REG)); 144 145 /* Allow all peripherals for normal world */ 146 io_write32(v + REG_TZPC_SMTA_DECPORT0_SET_REG, 0xbe); 147 io_write32(v + REG_TZPC_SMTA_DECPORT1_SET_REG, 0xff); 148 io_write32(v + REG_TZPC_SMTA_DECPORT2_SET_REG, 0x7f); 149 150 DMSG("SMTA_DECPORT0=%x", io_read32(v + REG_TZPC_SMTA_DECPORT0_STA_REG)); 151 DMSG("SMTA_DECPORT1=%x", io_read32(v + REG_TZPC_SMTA_DECPORT1_STA_REG)); 152 DMSG("SMTA_DECPORT2=%x", io_read32(v + REG_TZPC_SMTA_DECPORT2_STA_REG)); 153 } 154 #else 155 static inline void tzpc_init(void) 156 { 157 } 158 #endif /* SUNXI_TZPC_BASE */ 159 160 #ifndef CFG_WITH_ARM_TRUSTED_FW 161 void main_init_gic(void) 162 { 163 vaddr_t gicc_base; 164 vaddr_t gicd_base; 165 166 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC); 167 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC); 168 169 if (!gicc_base || !gicd_base) 170 panic(); 171 172 /* Initialize GIC */ 173 gic_init(&gic_data, gicc_base, gicd_base); 174 itr_init(&gic_data.chip); 175 } 176 177 void main_secondary_init_gic(void) 178 { 179 gic_cpu_init(&gic_data); 180 } 181 #endif 182 183 #ifdef ARM32 184 void plat_cpu_reset_late(void) 185 { 186 assert(!cpu_mmu_enabled()); 187 188 if (get_core_pos()) 189 return; 190 191 tzpc_init(); 192 } 193 #endif 194 195 /* 196 * Allwinner's A64 has TZC380 like controller called SMC that can 197 * be programmed to protect parts of DRAM from non-secure world. 198 */ 199 #ifdef CFG_TZC380 200 vaddr_t smc_base(void) 201 { 202 return (vaddr_t)phys_to_virt(SUNXI_SMC_BASE, MEM_AREA_IO_SEC); 203 } 204 205 static TEE_Result smc_init(void) 206 { 207 vaddr_t base = smc_base(); 208 209 if (!base) { 210 EMSG("smc not mapped"); 211 panic(); 212 } 213 214 tzc_init(base); 215 tzc_configure_region(0, 0x0, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_1G) | 216 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 217 tzc_configure_region(1, 0x0, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_32M) | 218 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_S_RW); 219 220 /* SoC specific bits */ 221 io_clrbits32(base + SMC_MASTER_BYPASS, SMC_MASTER_BYPASS_EN_MASK); 222 223 return TEE_SUCCESS; 224 } 225 226 driver_init(smc_init); 227 #endif /* CFG_TZC380 */ 228