1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #include <console.h> 7 #include <drivers/pl011.h> 8 #ifdef CFG_SPI 9 #include <drivers/pl022_spi.h> 10 #include <drivers/pl061_gpio.h> 11 #endif 12 #if defined(PLATFORM_FLAVOR_hikey) 13 #include <hikey_peripherals.h> 14 #endif 15 #include <initcall.h> 16 #include <io.h> 17 #include <kernel/generic_boot.h> 18 #include <kernel/panic.h> 19 #include <kernel/pm_stubs.h> 20 #include <mm/tee_pager.h> 21 #include <mm/core_memprot.h> 22 #include <platform_config.h> 23 #include <stdint.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 27 static void main_fiq(void); 28 29 static const struct thread_handlers handlers = { 30 .fast_smc = tee_entry_fast, 31 .nintr = main_fiq, 32 .cpu_on = cpu_on_handler, 33 .cpu_off = pm_do_nothing, 34 .cpu_suspend = pm_do_nothing, 35 .cpu_resume = pm_do_nothing, 36 .system_off = pm_do_nothing, 37 .system_reset = pm_do_nothing, 38 }; 39 40 static struct pl011_data console_data; 41 42 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 43 #if defined(PLATFORM_FLAVOR_hikey) 44 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE); 45 #endif 46 #if defined(CFG_SPI) && defined(PLATFORM_FLAVOR_hikey) 47 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE); 52 #endif 53 register_dynamic_shm(DRAM0_BASE, DRAM0_SIZE_NSEC); 54 #ifdef DRAM1_SIZE_NSEC 55 register_dynamic_shm(DRAM1_BASE, DRAM1_SIZE_NSEC); 56 #endif 57 #ifdef DRAM2_SIZE_NSEC 58 register_dynamic_shm(DRAM2_BASE, DRAM2_SIZE_NSEC); 59 #endif 60 61 const struct thread_handlers *generic_boot_get_handlers(void) 62 { 63 return &handlers; 64 } 65 66 static void main_fiq(void) 67 { 68 panic(); 69 } 70 71 void console_init(void) 72 { 73 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 74 CONSOLE_BAUDRATE); 75 register_serial_console(&console_data.chip); 76 } 77 78 #if defined(PLATFORM_FLAVOR_hikey) 79 #ifdef CFG_SPI 80 void spi_init(void) 81 { 82 uint32_t shifted_val, read_val; 83 vaddr_t peri_base = core_mmu_get_va(PERI_BASE, MEM_AREA_IO_NSEC); 84 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC); 85 vaddr_t pmx1_base = core_mmu_get_va(PMX1_BASE, MEM_AREA_IO_NSEC); 86 87 DMSG("take SPI0 out of reset\n"); 88 shifted_val = PERI_RST3_SSP; 89 /* 90 * no need to read PERI_SC_PERIPH_RSTDIS3 first 91 * as all the bits are processed and cleared after writing 92 */ 93 io_write32(peri_base + PERI_SC_PERIPH_RSTDIS3, shifted_val); 94 DMSG("PERI_SC_PERIPH_RSTDIS3: 0x%x\n", 95 io_read32(peri_base + PERI_SC_PERIPH_RSTDIS3)); 96 97 /* 98 * wait until the requested device is out of reset 99 * and ready to be used 100 */ 101 do { 102 read_val = io_read32(peri_base + PERI_SC_PERIPH_RSTSTAT3); 103 } while (read_val & shifted_val); 104 DMSG("PERI_SC_PERIPH_RSTSTAT3: 0x%x\n", read_val); 105 106 DMSG("enable SPI clock\n"); 107 /* 108 * no need to read PERI_SC_PERIPH_CLKEN3 first 109 * as all the bits are processed and cleared after writing 110 */ 111 shifted_val = PERI_CLK3_SSP; 112 io_write32(peri_base + PERI_SC_PERIPH_CLKEN3, shifted_val); 113 DMSG("PERI_SC_PERIPH_CLKEN3: 0x%x\n", 114 io_read32(peri_base + PERI_SC_PERIPH_CLKEN3)); 115 116 DMSG("PERI_SC_PERIPH_CLKSTAT3: 0x%x\n", 117 io_read32(peri_base + PERI_SC_PERIPH_CLKSTAT3)); 118 119 /* 120 * GPIO6_2 can be configured as PINMUX_GPIO, but as PINMUX_SPI, HW IP 121 * will control the chip select pin so we don't have to manually do it. 122 * The only concern is that the IP will pulse it between each packet, 123 * which might not work with certain clients. There seems to be no 124 * option to configure it to stay enabled for the total duration of the 125 * transfer. 126 * ref: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/CJACFAFG.html 127 */ 128 DMSG("configure gpio6 pins 0-3 as SPI\n"); 129 io_write32(pmx0_base + PMX0_IOMG104, PINMUX_SPI); 130 io_write32(pmx0_base + PMX0_IOMG105, PINMUX_SPI); 131 io_write32(pmx0_base + PMX0_IOMG106, PINMUX_SPI); 132 io_write32(pmx0_base + PMX0_IOMG107, PINMUX_SPI); 133 134 DMSG("configure gpio6 pins 0-3 as nopull\n"); 135 io_write32(pmx1_base + PMX1_IOCG104, PINCFG_NOPULL); 136 io_write32(pmx1_base + PMX1_IOCG105, PINCFG_NOPULL); 137 io_write32(pmx1_base + PMX1_IOCG106, PINCFG_NOPULL); 138 io_write32(pmx1_base + PMX1_IOCG107, PINCFG_NOPULL); 139 140 #ifdef CFG_SPI_TEST 141 spi_test(); 142 #endif 143 } 144 #endif 145 146 static TEE_Result peripherals_init(void) 147 { 148 vaddr_t pmussi_base = core_mmu_get_va(PMUSSI_BASE, MEM_AREA_IO_NSEC); 149 150 DMSG("enable LD021_1V8 source (pin 35) on LS connector\n"); 151 /* 152 * Mezzanine cards usually use this to source level shifters for 153 * UART, GPIO, SPI, I2C, etc so if not enabled, connected 154 * peripherals will not work either (during bootloader stage) 155 * until linux is booted. 156 */ 157 io_mask8(pmussi_base + PMUSSI_LDO21_REG_ADJ, PMUSSI_LDO21_REG_VL_1V8, 158 PMUSSI_LDO21_REG_VL_MASK); 159 io_write8(pmussi_base + PMUSSI_ENA_LDO17_22, PMUSSI_ENA_LDO21); 160 161 #ifdef CFG_SPI 162 spi_init(); 163 #endif 164 return TEE_SUCCESS; 165 } 166 167 driver_init(peripherals_init); 168 #endif /* PLATFORM_FLAVOR_hikey */ 169