1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright (c) 2016, Wind River Systems. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm32.h> 32 #include <console.h> 33 #include <drivers/cdns_uart.h> 34 #include <drivers/gic.h> 35 #include <io.h> 36 #include <kernel/generic_boot.h> 37 #include <kernel/misc.h> 38 #include <kernel/panic.h> 39 #include <kernel/pm_stubs.h> 40 #include <kernel/tz_ssvce_pl310.h> 41 #include <mm/core_mmu.h> 42 #include <mm/core_memprot.h> 43 #include <platform_config.h> 44 #include <platform_smc.h> 45 #include <stdint.h> 46 #include <tee/entry_fast.h> 47 #include <tee/entry_std.h> 48 49 static void main_fiq(void); 50 51 static const struct thread_handlers handlers = { 52 .nintr = main_fiq, 53 .cpu_on = pm_panic, 54 .cpu_off = pm_panic, 55 .cpu_suspend = pm_panic, 56 .cpu_resume = pm_panic, 57 .system_off = pm_panic, 58 .system_reset = pm_panic, 59 }; 60 61 static struct gic_data gic_data; 62 static struct cdns_uart_data console_data; 63 64 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 65 CORE_MMU_PGDIR_SIZE); 66 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 67 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE); 68 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SLCR_BASE, CORE_MMU_PGDIR_SIZE); 69 70 const struct thread_handlers *generic_boot_get_handlers(void) 71 { 72 return &handlers; 73 } 74 75 static void main_fiq(void) 76 { 77 panic(); 78 } 79 80 void plat_cpu_reset_late(void) 81 { 82 if (!get_core_pos()) { 83 /* primary core */ 84 #if defined(CFG_BOOT_SECONDARY_REQUEST) 85 /* set secondary entry address and release core */ 86 io_write32(SECONDARY_ENTRY_DROP, TEE_LOAD_ADDR); 87 dsb(); 88 sev(); 89 #endif 90 91 /* SCU config */ 92 io_write32(SCU_BASE + SCU_INV_SEC, SCU_INV_CTRL_INIT); 93 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_CTRL_INIT); 94 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_CTRL_INIT); 95 96 /* SCU enable */ 97 io_setbits32(SCU_BASE + SCU_CTRL, 0x1); 98 99 /* NS Access control */ 100 io_write32(SECURITY2_SDIO0, ACCESS_BITS_ALL); 101 io_write32(SECURITY3_SDIO1, ACCESS_BITS_ALL); 102 io_write32(SECURITY4_QSPI, ACCESS_BITS_ALL); 103 io_write32(SECURITY6_APB_SLAVES, ACCESS_BITS_ALL); 104 105 io_write32(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK); 106 107 io_write32(SLCR_TZ_DDR_RAM, ACCESS_BITS_ALL); 108 io_write32(SLCR_TZ_DMA_NS, ACCESS_BITS_ALL); 109 io_write32(SLCR_TZ_DMA_IRQ_NS, ACCESS_BITS_ALL); 110 io_write32(SLCR_TZ_DMA_PERIPH_NS, ACCESS_BITS_ALL); 111 io_write32(SLCR_TZ_GEM, ACCESS_BITS_ALL); 112 io_write32(SLCR_TZ_SDIO, ACCESS_BITS_ALL); 113 io_write32(SLCR_TZ_USB, ACCESS_BITS_ALL); 114 115 io_write32(SLCR_LOCK, SLCR_LOCK_MAGIC); 116 } 117 } 118 119 void console_init(void) 120 { 121 cdns_uart_init(&console_data, CONSOLE_UART_BASE, 0, 0); 122 register_serial_console(&console_data.chip); 123 } 124 125 vaddr_t pl310_base(void) 126 { 127 static void *va; 128 129 if (cpu_mmu_enabled()) { 130 if (!va) 131 va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); 132 return (vaddr_t)va; 133 } 134 return PL310_BASE; 135 } 136 137 void arm_cl2_config(vaddr_t pl310_base) 138 { 139 /* Disable PL310 */ 140 io_write32(pl310_base + PL310_CTRL, 0); 141 142 /* 143 * Xilinx AR#54190 recommends setting L2C RAM in SLCR 144 * to 0x00020202 for proper cache operations. 145 */ 146 io_write32(SLCR_L2C_RAM, SLCR_L2C_RAM_VALUE); 147 148 io_write32(pl310_base + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); 149 io_write32(pl310_base + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); 150 io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); 151 io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); 152 io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); 153 154 /* invalidate all cache ways */ 155 arm_cl2_invbyway(pl310_base); 156 } 157 158 void arm_cl2_enable(vaddr_t pl310_base) 159 { 160 uint32_t val; 161 162 /* Enable PL310 ctrl -> only set lsb bit */ 163 io_write32(pl310_base + PL310_CTRL, 1); 164 165 /* if L2 FLZW enable, enable in L1 */ 166 val = io_read32(pl310_base + PL310_AUX_CTRL); 167 if (val & 1) 168 write_actlr(read_actlr() | (1 << 3)); 169 } 170 171 void main_init_gic(void) 172 { 173 vaddr_t gicc_base; 174 vaddr_t gicd_base; 175 176 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 177 MEM_AREA_IO_SEC); 178 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 179 MEM_AREA_IO_SEC); 180 181 if (!gicc_base || !gicd_base) 182 panic(); 183 184 /* Initialize GIC */ 185 gic_init(&gic_data, gicc_base, gicd_base); 186 itr_init(&gic_data.chip); 187 } 188 189 void main_secondary_init_gic(void) 190 { 191 gic_cpu_init(&gic_data); 192 } 193 194 static vaddr_t slcr_access_range[] = { 195 0x004, 0x008, /* lock, unlock */ 196 0x100, 0x1FF, /* PLL */ 197 0x200, 0x2FF, /* Reset */ 198 0xA00, 0xAFF /* L2C */ 199 }; 200 201 static uint32_t write_slcr(uint32_t addr, uint32_t val) 202 { 203 uint32_t i; 204 205 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 206 if (addr >= slcr_access_range[i] && 207 addr <= slcr_access_range[i+1]) { 208 static vaddr_t va; 209 210 if (!va) 211 va = (vaddr_t)phys_to_virt(SLCR_BASE, 212 MEM_AREA_IO_SEC); 213 io_write32(va + addr, val); 214 return OPTEE_SMC_RETURN_OK; 215 } 216 } 217 return OPTEE_SMC_RETURN_EBADADDR; 218 } 219 220 static uint32_t read_slcr(uint32_t addr, uint32_t *val) 221 { 222 uint32_t i; 223 224 for (i = 0; i < ARRAY_SIZE(slcr_access_range); i += 2) { 225 if (addr >= slcr_access_range[i] && 226 addr <= slcr_access_range[i+1]) { 227 static vaddr_t va; 228 229 if (!va) 230 va = (vaddr_t)phys_to_virt(SLCR_BASE, 231 MEM_AREA_IO_SEC); 232 *val = io_read32(va + addr); 233 return OPTEE_SMC_RETURN_OK; 234 } 235 } 236 return OPTEE_SMC_RETURN_EBADADDR; 237 } 238 239 /* Overriding the default __weak tee_entry_fast() */ 240 void tee_entry_fast(struct thread_smc_args *args) 241 { 242 switch (args->a0) { 243 case ZYNQ7K_SMC_SLCR_WRITE: 244 args->a0 = write_slcr(args->a1, args->a2); 245 break; 246 case ZYNQ7K_SMC_SLCR_READ: 247 args->a0 = read_slcr(args->a1, &args->a2); 248 break; 249 default: 250 __tee_entry_fast(args); 251 break; 252 } 253 } 254