1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6#include <platform_config.h> 7 8#include <arm64_macros.S> 9#include <arm.h> 10#include <asm.S> 11#include <generated/asm-defines.h> 12#include <keep.h> 13#include <sm/optee_smc.h> 14#include <sm/teesmc_opteed.h> 15#include <sm/teesmc_opteed_macros.h> 16 17 /* 18 * Setup SP_EL0 and SPEL1, SP will be set to SP_EL0. 19 * SP_EL0 is assigned stack_tmp_export + cpu_id * stack_tmp_stride 20 * SP_EL1 is assigned thread_core_local[cpu_id] 21 */ 22 .macro set_sp 23 bl __get_core_pos 24 cmp x0, #CFG_TEE_CORE_NB_CORE 25 /* Unsupported CPU, park it before it breaks something */ 26 bge unhandled_cpu 27 adr x1, stack_tmp_stride 28 ldr w1, [x1] 29 mul x1, x0, x1 30 adrp x0, stack_tmp_export 31 add x0, x0, :lo12:stack_tmp_export 32 ldr x0, [x0] 33 msr spsel, #0 34 add sp, x1, x0 35 bl thread_get_core_local 36 msr spsel, #1 37 mov sp, x0 38 msr spsel, #0 39 .endm 40 41 .macro set_sctlr_el1 42 mrs x0, sctlr_el1 43 orr x0, x0, #SCTLR_I 44 orr x0, x0, #SCTLR_SA 45 orr x0, x0, #SCTLR_SPAN 46#if defined(CFG_CORE_RWDATA_NOEXEC) 47 orr x0, x0, #SCTLR_WXN 48#endif 49#if defined(CFG_SCTLR_ALIGNMENT_CHECK) 50 orr x0, x0, #SCTLR_A 51#else 52 bic x0, x0, #SCTLR_A 53#endif 54 msr sctlr_el1, x0 55 .endm 56 57FUNC _start , : 58 mov x19, x0 /* Save pagable part address */ 59#if defined(CFG_DT_ADDR) 60 ldr x20, =CFG_DT_ADDR 61#else 62 mov x20, x2 /* Save DT address */ 63#endif 64 65 adr x0, reset_vect_table 66 msr vbar_el1, x0 67 isb 68 69 set_sctlr_el1 70 isb 71 72#ifdef CFG_WITH_PAGER 73 /* 74 * Move init code into correct location and move hashes to a 75 * temporary safe location until the heap is initialized. 76 * 77 * The binary is built as: 78 * [Pager code, rodata and data] : In correct location 79 * [Init code and rodata] : Should be copied to __init_start 80 * [struct boot_embdata + data] : Should be saved before 81 * initializing pager, first uint32_t tells the length of the data 82 */ 83 adr x0, __init_start /* dst */ 84 adr x1, __data_end /* src */ 85 adr x2, __init_end 86 sub x2, x2, x0 /* init len */ 87 ldr w4, [x1, x2] /* length of hashes etc */ 88 add x2, x2, x4 /* length of init and hashes etc */ 89 /* Copy backwards (as memmove) in case we're overlapping */ 90 add x0, x0, x2 /* __init_start + len */ 91 add x1, x1, x2 /* __data_end + len */ 92 adr x3, cached_mem_end 93 str x0, [x3] 94 adr x2, __init_start 95copy_init: 96 ldp x3, x4, [x1, #-16]! 97 stp x3, x4, [x0, #-16]! 98 cmp x0, x2 99 b.gt copy_init 100#else 101 /* 102 * The binary is built as: 103 * [Core, rodata and data] : In correct location 104 * [struct boot_embdata + data] : Should be moved to __end, first 105 * uint32_t tells the length of the struct + data 106 */ 107 adr_l x0, __end /* dst */ 108 adr_l x1, __data_end /* src */ 109 ldr w2, [x1] /* struct boot_embdata::total_len */ 110 /* Copy backwards (as memmove) in case we're overlapping */ 111 add x0, x0, x2 112 add x1, x1, x2 113 adr x3, cached_mem_end 114 str x0, [x3] 115 adr_l x2, __end 116 117copy_init: 118 ldp x3, x4, [x1, #-16]! 119 stp x3, x4, [x0, #-16]! 120 cmp x0, x2 121 b.gt copy_init 122#endif 123 124 /* 125 * Clear .bss, this code obviously depends on the linker keeping 126 * start/end of .bss at least 8 byte aligned. 127 */ 128 adr_l x0, __bss_start 129 adr_l x1, __bss_end 130clear_bss: 131 str xzr, [x0], #8 132 cmp x0, x1 133 b.lt clear_bss 134 135#ifdef CFG_VIRTUALIZATION 136 /* 137 * Clear .nex_bss, this code obviously depends on the linker keeping 138 * start/end of .bss at least 8 byte aligned. 139 */ 140 adr x0, __nex_bss_start 141 adr x1, __nex_bss_end 142clear_nex_bss: 143 str xzr, [x0], #8 144 cmp x0, x1 145 b.lt clear_nex_bss 146#endif 147 148 /* Setup SP_EL0 and SP_EL1, SP will be set to SP_EL0 */ 149 set_sp 150 151 /* Enable aborts now that we can receive exceptions */ 152 msr daifclr, #DAIFBIT_ABT 153 154 /* 155 * Invalidate dcache for all memory used during initialization to 156 * avoid nasty surprices when the cache is turned on. We must not 157 * invalidate memory not used by OP-TEE since we may invalidate 158 * entries used by for instance ARM Trusted Firmware. 159 */ 160 adr_l x0, __text_start 161 ldr x1, cached_mem_end 162 sub x1, x1, x0 163 bl dcache_cleaninv_range 164 165 /* Enable Console */ 166 bl console_init 167 168#ifdef CFG_CORE_ASLR 169 mov x0, x20 170 bl get_aslr_seed 171#else 172 mov x0, #0 173#endif 174 175 adr x1, boot_mmu_config 176 bl core_init_mmu_map 177 178#ifdef CFG_CORE_ASLR 179 /* 180 * Process relocation information again updating for the new 181 * offset. We're doing this now before MMU is enabled as some of 182 * the memory will become write protected. 183 */ 184 ldr x0, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET 185 /* 186 * Update cached_mem_end address with load offset since it was 187 * calculated before relocation. 188 */ 189 adr x5, cached_mem_end 190 ldr x6, [x5] 191 add x6, x6, x0 192 str x6, [x5] 193 bl relocate 194#endif 195 196 bl __get_core_pos 197 bl enable_mmu 198#ifdef CFG_CORE_ASLR 199 /* 200 * Reinitialize console, since register_serial_console() has 201 * previously registered a PA and with ASLR the VA is different 202 * from the PA. 203 */ 204 bl console_init 205#endif 206 207 mov x0, x19 /* pagable part address */ 208 mov x1, #-1 209 mov x2, x20 /* DT address */ 210 bl boot_init_primary 211 212 /* 213 * In case we've touched memory that secondary CPUs will use before 214 * they have turned on their D-cache, clean and invalidate the 215 * D-cache before exiting to normal world. 216 */ 217 adr_l x0, __text_start 218 ldr x1, cached_mem_end 219 sub x1, x1, x0 220 bl dcache_cleaninv_range 221 222 223 /* 224 * Clear current thread id now to allow the thread to be reused on 225 * next entry. Matches the thread_init_boot_thread in 226 * boot.c. 227 */ 228#ifndef CFG_VIRTUALIZATION 229 bl thread_clr_boot_thread 230#endif 231 232 /* 233 * Pass the vector address returned from main_init 234 * Compensate for the load offset since cpu_on_handler() is 235 * called with MMU off. 236 */ 237 ldr x0, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET 238 adr x1, thread_vector_table 239 sub x1, x1, x0 240 mov x0, #TEESMC_OPTEED_RETURN_ENTRY_DONE 241 smc #0 242 b . /* SMC should not return */ 243END_FUNC _start 244DECLARE_KEEP_INIT _start 245 246 .balign 8 247LOCAL_DATA cached_mem_end , : 248 .skip 8 249END_DATA cached_mem_end 250 251#ifdef CFG_CORE_ASLR 252LOCAL_FUNC relocate , : 253 /* x0 holds load offset */ 254#ifdef CFG_WITH_PAGER 255 adr_l x6, __init_end 256#else 257 adr_l x6, __end 258#endif 259 ldp w2, w3, [x6, #BOOT_EMBDATA_RELOC_OFFSET] 260 261 mov_imm x1, TEE_RAM_START 262 add x2, x2, x6 /* start of relocations */ 263 add x3, x3, x2 /* end of relocations */ 264 265 /* 266 * Relocations are not formatted as Rela64, instead they are in a 267 * compressed format created by get_reloc_bin() in 268 * scripts/gen_tee_bin.py 269 * 270 * All the R_AARCH64_RELATIVE relocations are translated into a 271 * list list of 32-bit offsets from TEE_RAM_START. At each address 272 * a 64-bit value pointed out which increased with the load offset. 273 */ 274 275#ifdef CFG_WITH_PAGER 276 /* 277 * With pager enabled we can only relocate the pager and init 278 * parts, the rest has to be done when a page is populated. 279 */ 280 sub x6, x6, x1 281#endif 282 283 b 2f 284 /* Loop over the relocation addresses and process all entries */ 2851: ldr w4, [x2], #4 286#ifdef CFG_WITH_PAGER 287 /* Skip too large addresses */ 288 cmp x4, x6 289 b.ge 2f 290#endif 291 add x4, x4, x1 292 ldr x5, [x4] 293 add x5, x5, x0 294 str x5, [x4] 295 2962: cmp x2, x3 297 b.ne 1b 298 299 ret 300END_FUNC relocate 301#endif 302 303/* 304 * void enable_mmu(unsigned long core_pos); 305 * 306 * This function depends on being mapped with in the identity map where 307 * physical address and virtual address is the same. After MMU has been 308 * enabled the instruction pointer will be updated to execute as the new 309 * offset instead. Stack pointers and the return address are updated. 310 */ 311LOCAL_FUNC enable_mmu , : , .identity_map 312 adr x1, boot_mmu_config 313 load_xregs x1, 0, 2, 6 314 /* 315 * x0 = core_pos 316 * x2 = tcr_el1 317 * x3 = mair_el1 318 * x4 = ttbr0_el1_base 319 * x5 = ttbr0_core_offset 320 * x6 = load_offset 321 */ 322 msr tcr_el1, x2 323 msr mair_el1, x3 324 325 /* 326 * ttbr0_el1 = ttbr0_el1_base + ttbr0_core_offset * core_pos 327 */ 328 madd x1, x5, x0, x4 329 msr ttbr0_el1, x1 330 msr ttbr1_el1, xzr 331 isb 332 333 /* Invalidate TLB */ 334 tlbi vmalle1 335 336 /* 337 * Make sure translation table writes have drained into memory and 338 * the TLB invalidation is complete. 339 */ 340 dsb sy 341 isb 342 343 /* Enable the MMU */ 344 mrs x1, sctlr_el1 345 orr x1, x1, #SCTLR_M 346 msr sctlr_el1, x1 347 isb 348 349 /* Update vbar */ 350 mrs x1, vbar_el1 351 add x1, x1, x6 352 msr vbar_el1, x1 353 isb 354 355 /* Invalidate instruction cache and branch predictor */ 356 ic iallu 357 isb 358 359 /* Enable I and D cache */ 360 mrs x1, sctlr_el1 361 orr x1, x1, #SCTLR_I 362 orr x1, x1, #SCTLR_C 363 msr sctlr_el1, x1 364 isb 365 366 /* Adjust stack pointers and return address */ 367 msr spsel, #1 368 add sp, sp, x6 369 msr spsel, #0 370 add sp, sp, x6 371 add x30, x30, x6 372 373 ret 374END_FUNC enable_mmu 375 376 .balign 8 377DATA boot_mmu_config , : /* struct core_mmu_config */ 378 .skip CORE_MMU_CONFIG_SIZE 379END_DATA boot_mmu_config 380 381FUNC cpu_on_handler , : 382 mov x19, x0 383 mov x20, x1 384 mov x21, x30 385 386 adr x0, reset_vect_table 387 msr vbar_el1, x0 388 isb 389 390 set_sctlr_el1 391 isb 392 393 /* Enable aborts now that we can receive exceptions */ 394 msr daifclr, #DAIFBIT_ABT 395 396 bl __get_core_pos 397 bl enable_mmu 398 399 /* Setup SP_EL0 and SP_EL1, SP will be set to SP_EL0 */ 400 set_sp 401 402 mov x0, x19 403 mov x1, x20 404 mov x30, x21 405 b boot_cpu_on_handler 406END_FUNC cpu_on_handler 407DECLARE_KEEP_PAGER cpu_on_handler 408 409LOCAL_FUNC unhandled_cpu , : 410 wfi 411 b unhandled_cpu 412END_FUNC unhandled_cpu 413 414 /* 415 * This macro verifies that the a given vector doesn't exceed the 416 * architectural limit of 32 instructions. This is meant to be placed 417 * immedately after the last instruction in the vector. It takes the 418 * vector entry as the parameter 419 */ 420 .macro check_vector_size since 421 .if (. - \since) > (32 * 4) 422 .error "Vector exceeds 32 instructions" 423 .endif 424 .endm 425 426 .section .identity_map, "ax", %progbits 427 .align 11 428LOCAL_FUNC reset_vect_table , :, .identity_map 429 /* ----------------------------------------------------- 430 * Current EL with SP0 : 0x0 - 0x180 431 * ----------------------------------------------------- 432 */ 433SynchronousExceptionSP0: 434 b SynchronousExceptionSP0 435 check_vector_size SynchronousExceptionSP0 436 437 .align 7 438IrqSP0: 439 b IrqSP0 440 check_vector_size IrqSP0 441 442 .align 7 443FiqSP0: 444 b FiqSP0 445 check_vector_size FiqSP0 446 447 .align 7 448SErrorSP0: 449 b SErrorSP0 450 check_vector_size SErrorSP0 451 452 /* ----------------------------------------------------- 453 * Current EL with SPx: 0x200 - 0x380 454 * ----------------------------------------------------- 455 */ 456 .align 7 457SynchronousExceptionSPx: 458 b SynchronousExceptionSPx 459 check_vector_size SynchronousExceptionSPx 460 461 .align 7 462IrqSPx: 463 b IrqSPx 464 check_vector_size IrqSPx 465 466 .align 7 467FiqSPx: 468 b FiqSPx 469 check_vector_size FiqSPx 470 471 .align 7 472SErrorSPx: 473 b SErrorSPx 474 check_vector_size SErrorSPx 475 476 /* ----------------------------------------------------- 477 * Lower EL using AArch64 : 0x400 - 0x580 478 * ----------------------------------------------------- 479 */ 480 .align 7 481SynchronousExceptionA64: 482 b SynchronousExceptionA64 483 check_vector_size SynchronousExceptionA64 484 485 .align 7 486IrqA64: 487 b IrqA64 488 check_vector_size IrqA64 489 490 .align 7 491FiqA64: 492 b FiqA64 493 check_vector_size FiqA64 494 495 .align 7 496SErrorA64: 497 b SErrorA64 498 check_vector_size SErrorA64 499 500 /* ----------------------------------------------------- 501 * Lower EL using AArch32 : 0x0 - 0x180 502 * ----------------------------------------------------- 503 */ 504 .align 7 505SynchronousExceptionA32: 506 b SynchronousExceptionA32 507 check_vector_size SynchronousExceptionA32 508 509 .align 7 510IrqA32: 511 b IrqA32 512 check_vector_size IrqA32 513 514 .align 7 515FiqA32: 516 b FiqA32 517 check_vector_size FiqA32 518 519 .align 7 520SErrorA32: 521 b SErrorA32 522 check_vector_size SErrorA32 523 524END_FUNC reset_vect_table 525