xref: /optee_os/core/arch/arm/plat-hisilicon/main.c (revision 2dd2ca5f39e6dd144a8be81f5e00badf79d362fe)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (c) 2019, HiSilicon Technologies Co., Ltd.
4  */
5 
6 #include <console.h>
7 #include <drivers/gic.h>
8 #include <drivers/pl011.h>
9 #include <kernel/generic_boot.h>
10 #include <kernel/panic.h>
11 #include <kernel/pm_stubs.h>
12 #include <mm/tee_pager.h>
13 #include <mm/core_memprot.h>
14 #include <platform_config.h>
15 #include <stdint.h>
16 #include <tee/entry_std.h>
17 #include <tee/entry_fast.h>
18 
19 static void main_fiq(void);
20 
21 static const struct thread_handlers handlers = {
22 	.fast_smc = tee_entry_fast,
23 	.nintr = main_fiq,
24 	.cpu_on = pm_panic,
25 	.cpu_off = pm_panic,
26 	.cpu_suspend = pm_panic,
27 	.cpu_resume = pm_panic,
28 	.system_off = pm_panic,
29 	.system_reset = pm_panic,
30 };
31 
32 static struct pl011_data console_data;
33 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
34 #ifdef BOOTSRAM_BASE
35 register_phys_mem(MEM_AREA_IO_SEC, BOOTSRAM_BASE, BOOTSRAM_SIZE);
36 #endif
37 #ifdef CPU_CRG_BASE
38 register_phys_mem(MEM_AREA_IO_SEC, CPU_CRG_BASE, CPU_CRG_SIZE);
39 #endif
40 #ifdef SYS_CTRL_BASE
41 register_phys_mem(MEM_AREA_IO_SEC, SYS_CTRL_BASE, SYS_CTRL_SIZE);
42 #endif
43 
44 const struct thread_handlers *generic_boot_get_handlers(void)
45 {
46 	return &handlers;
47 }
48 
49 static void main_fiq(void)
50 {
51 	panic();
52 }
53 
54 void console_init(void)
55 {
56 	pl011_init(&console_data, CONSOLE_UART_BASE,
57 		CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
58 	register_serial_console(&console_data.chip);
59 }
60