1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/stm32_etzpc.h> 11 #include <drivers/stm32_uart.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <dt-bindings/clock/stm32mp1-clks.h> 14 #include <kernel/generic_boot.h> 15 #include <kernel/dt.h> 16 #include <kernel/misc.h> 17 #include <kernel/panic.h> 18 #include <kernel/pm_stubs.h> 19 #include <kernel/spinlock.h> 20 #include <mm/core_memprot.h> 21 #include <platform_config.h> 22 #include <sm/psci.h> 23 #include <stm32_util.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 #include <trace.h> 27 28 #ifdef CFG_WITH_NSEC_GPIOS 29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIOS_NSEC_BASE, GPIOS_NSEC_SIZE); 30 #endif 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C4_BASE, SMALL_PAGE_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, I2C6_BASE, SMALL_PAGE_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, RNG1_BASE, SMALL_PAGE_SIZE); 34 #ifdef CFG_WITH_NSEC_UARTS 35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART1_BASE, SMALL_PAGE_SIZE); 36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART2_BASE, SMALL_PAGE_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART3_BASE, SMALL_PAGE_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, USART6_BASE, SMALL_PAGE_SIZE); 41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE); 42 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE); 43 #endif 44 45 register_phys_mem_pgdir(MEM_AREA_IO_SEC, BSEC_BASE, SMALL_PAGE_SIZE); 46 register_phys_mem_pgdir(MEM_AREA_IO_SEC, ETZPC_BASE, SMALL_PAGE_SIZE); 47 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 48 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GPIOZ_BASE, SMALL_PAGE_SIZE); 49 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C4_BASE, SMALL_PAGE_SIZE); 50 register_phys_mem_pgdir(MEM_AREA_IO_SEC, I2C6_BASE, SMALL_PAGE_SIZE); 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PWR_BASE, SMALL_PAGE_SIZE); 52 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RCC_BASE, SMALL_PAGE_SIZE); 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, RNG1_BASE, SMALL_PAGE_SIZE); 54 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TAMP_BASE, SMALL_PAGE_SIZE); 55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, USART1_BASE, SMALL_PAGE_SIZE); 56 57 static void main_fiq(void); 58 59 static const struct thread_handlers handlers = { 60 .fast_smc = tee_entry_fast, 61 .nintr = main_fiq, 62 .cpu_on = pm_panic, 63 .cpu_off = pm_panic, 64 .cpu_suspend = pm_panic, 65 .cpu_resume = pm_panic, 66 .system_off = pm_panic, 67 .system_reset = pm_panic, 68 }; 69 70 const struct thread_handlers *generic_boot_get_handlers(void) 71 { 72 return &handlers; 73 } 74 75 #define _ID2STR(id) (#id) 76 #define ID2STR(id) _ID2STR(id) 77 78 static TEE_Result platform_banner(void) 79 { 80 #ifdef CFG_EMBED_DTB 81 IMSG("Platform stm32mp1: flavor %s - DT %s", 82 ID2STR(PLATFORM_FLAVOR), 83 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 84 #else 85 IMSG("Platform stm32mp1: flavor %s - no device tree", 86 ID2STR(PLATFORM_FLAVOR)); 87 #endif 88 89 return TEE_SUCCESS; 90 } 91 service_init(platform_banner); 92 93 /* 94 * Console 95 * 96 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 97 * trace console. Value 0 disables the early console. 98 * 99 * We cannot use the generic serial_console support since probing 100 * the console requires the platform clock driver to be already 101 * up and ready which is done only once service_init are completed. 102 */ 103 static struct stm32_uart_pdata console_data; 104 105 void console_init(void) 106 { 107 /* Early console initialization before MMU setup */ 108 struct uart { 109 paddr_t pa; 110 bool secure; 111 } uarts[] = { 112 [0] = { .pa = 0 }, 113 [1] = { .pa = USART1_BASE, .secure = true, }, 114 [2] = { .pa = USART2_BASE, .secure = false, }, 115 [3] = { .pa = USART3_BASE, .secure = false, }, 116 [4] = { .pa = UART4_BASE, .secure = false, }, 117 [5] = { .pa = UART5_BASE, .secure = false, }, 118 [6] = { .pa = USART6_BASE, .secure = false, }, 119 [7] = { .pa = UART7_BASE, .secure = false, }, 120 [8] = { .pa = UART8_BASE, .secure = false, }, 121 }; 122 123 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 124 assert(!cpu_mmu_enabled()); 125 126 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 127 return; 128 129 /* No clock yet bound to the UART console */ 130 console_data.clock = DT_INFO_INVALID_CLOCK; 131 132 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 133 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 134 135 register_serial_console(&console_data.chip); 136 137 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 138 } 139 140 #ifdef CFG_DT 141 static TEE_Result init_console_from_dt(void) 142 { 143 struct stm32_uart_pdata *pd = NULL; 144 void *fdt = NULL; 145 int node = 0; 146 TEE_Result res = TEE_ERROR_GENERIC; 147 148 fdt = get_embedded_dt(); 149 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 150 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 151 fdt = get_external_dt(); 152 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 153 if (res == TEE_ERROR_ITEM_NOT_FOUND) 154 return TEE_SUCCESS; 155 if (res != TEE_SUCCESS) 156 return res; 157 } 158 159 pd = stm32_uart_init_from_dt_node(fdt, node); 160 if (!pd) { 161 IMSG("DTB disables console"); 162 register_serial_console(NULL); 163 return TEE_SUCCESS; 164 } 165 166 /* Replace early console with the new one */ 167 console_flush(); 168 console_data = *pd; 169 free(pd); 170 register_serial_console(&console_data.chip); 171 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 172 173 return TEE_SUCCESS; 174 } 175 176 /* Probe console from DT once clock inits (service init level) are completed */ 177 service_init_late(init_console_from_dt); 178 #endif 179 180 /* 181 * GIC init, used also for primary/secondary boot core wake completion 182 */ 183 static struct gic_data gic_data; 184 185 static void main_fiq(void) 186 { 187 gic_it_handle(&gic_data); 188 } 189 190 void main_init_gic(void) 191 { 192 assert(cpu_mmu_enabled()); 193 194 gic_init(&gic_data, get_gicc_base(), get_gicd_base()); 195 itr_init(&gic_data.chip); 196 197 stm32mp_register_online_cpu(); 198 } 199 200 void main_secondary_init_gic(void) 201 { 202 gic_cpu_init(&gic_data); 203 204 stm32mp_register_online_cpu(); 205 } 206 207 #ifndef CFG_EMBED_DTB 208 static TEE_Result init_stm32mp1_drivers(void) 209 { 210 /* Without secure DTB support, some drivers must be inited */ 211 stm32_etzpc_init(ETZPC_BASE); 212 213 return TEE_SUCCESS; 214 } 215 driver_init(init_stm32mp1_drivers); 216 #endif /*!CFG_EMBED_DTB*/ 217 218 /* Platform initializations once all drivers are ready */ 219 static TEE_Result init_late_stm32mp1_drivers(void) 220 { 221 /* Secure internal memories for the platform, once ETZPC is ready */ 222 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 223 etzpc_lock_tzma(0); 224 etzpc_configure_tzma(1, ETZPC_TZMA_ALL_SECURE); 225 etzpc_lock_tzma(1); 226 227 /* Static secure DECPROT configuration */ 228 etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); 229 etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); 230 etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID, ETZPC_DECPROT_S_RW); 231 etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_S_RW); 232 etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_S_RW); 233 etzpc_lock_decprot(STM32MP1_ETZPC_STGENC_ID); 234 etzpc_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID); 235 etzpc_lock_decprot(STM32MP1_ETZPC_IWDG1_ID); 236 etzpc_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID); 237 etzpc_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID); 238 /* Static non-secure DECPROT configuration */ 239 etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID, ETZPC_DECPROT_NS_RW); 240 etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID, ETZPC_DECPROT_NS_RW); 241 etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID, ETZPC_DECPROT_NS_RW); 242 etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID, ETZPC_DECPROT_NS_RW); 243 /* Release few resource to the non-secure world */ 244 etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID, ETZPC_DECPROT_NS_RW); 245 etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID, ETZPC_DECPROT_NS_RW); 246 etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID, ETZPC_DECPROT_NS_RW); 247 248 return TEE_SUCCESS; 249 } 250 driver_init_late(init_late_stm32mp1_drivers); 251 252 vaddr_t get_gicc_base(void) 253 { 254 struct io_pa_va base = { .pa = GIC_BASE + GICC_OFFSET }; 255 256 return io_pa_or_va_secure(&base); 257 } 258 259 vaddr_t get_gicd_base(void) 260 { 261 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 262 263 return io_pa_or_va_secure(&base); 264 } 265 266 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 267 { 268 cfg->base = BSEC_BASE; 269 cfg->upper_start = STM32MP1_UPPER_OTP_START; 270 cfg->max_id = STM32MP1_OTP_MAX_ID; 271 cfg->closed_device_id = DATA0_OTP; 272 cfg->closed_device_position = DATA0_OTP_SECURED_POS; 273 } 274 275 bool stm32mp_is_closed_device(void) 276 { 277 uint32_t otp = 0; 278 TEE_Result result = TEE_ERROR_GENERIC; 279 280 /* Non closed_device platform expects fuse well programmed to 0 */ 281 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 282 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 283 return false; 284 285 return true; 286 } 287 288 uint32_t may_spin_lock(unsigned int *lock) 289 { 290 if (!lock || !cpu_mmu_enabled()) 291 return 0; 292 293 return cpu_spin_lock_xsave(lock); 294 } 295 296 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 297 { 298 if (!lock || !cpu_mmu_enabled()) 299 return; 300 301 cpu_spin_unlock_xrestore(lock, exceptions); 302 } 303 304 static vaddr_t stm32_tamp_base(void) 305 { 306 static struct io_pa_va base = { .pa = TAMP_BASE }; 307 308 return io_pa_or_va_secure(&base); 309 } 310 311 static vaddr_t bkpreg_base(void) 312 { 313 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 314 } 315 316 vaddr_t stm32mp_bkpreg(unsigned int idx) 317 { 318 return bkpreg_base() + (idx * sizeof(uint32_t)); 319 } 320 321 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 322 { 323 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 324 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 325 326 /* Get non-secure mapping address for GPIOZ */ 327 if (bank == GPIO_BANK_Z) 328 return io_pa_or_va_nsec(&gpioz_base); 329 330 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 331 assert(bank <= GPIO_BANK_K); 332 333 return io_pa_or_va_nsec(&gpios_nsec_base) + (bank * GPIO_BANK_OFFSET); 334 } 335 336 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 337 { 338 if (bank == GPIO_BANK_Z) 339 return 0; 340 341 assert(bank <= GPIO_BANK_K); 342 return bank * GPIO_BANK_OFFSET; 343 } 344 345 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 346 { 347 if (bank == GPIO_BANK_Z) 348 return GPIOZ; 349 350 assert(bank <= GPIO_BANK_K); 351 return GPIOA + bank; 352 } 353