1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/pl011.h> 11 #include <drivers/tzc400.h> 12 #include <initcall.h> 13 #include <keep.h> 14 #include <kernel/generic_boot.h> 15 #include <kernel/misc.h> 16 #include <kernel/panic.h> 17 #include <kernel/pm_stubs.h> 18 #include <kernel/tee_time.h> 19 #include <mm/core_memprot.h> 20 #include <mm/core_mmu.h> 21 #include <platform_config.h> 22 #include <sm/psci.h> 23 #include <stdint.h> 24 #include <string.h> 25 #include <tee/entry_fast.h> 26 #include <tee/entry_std.h> 27 #include <trace.h> 28 29 static void main_fiq(void); 30 31 static const struct thread_handlers handlers = { 32 .nintr = main_fiq, 33 #if defined(CFG_WITH_ARM_TRUSTED_FW) 34 .cpu_on = cpu_on_handler, 35 .cpu_off = pm_do_nothing, 36 .cpu_suspend = pm_do_nothing, 37 .cpu_resume = pm_do_nothing, 38 .system_off = pm_do_nothing, 39 .system_reset = pm_do_nothing, 40 #else 41 .cpu_on = pm_panic, 42 .cpu_off = pm_panic, 43 .cpu_suspend = pm_panic, 44 .cpu_resume = pm_panic, 45 .system_off = pm_panic, 46 .system_reset = pm_panic, 47 #endif 48 }; 49 50 static struct gic_data gic_data __nex_bss; 51 static struct pl011_data console_data __nex_bss; 52 53 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 54 #if defined(PLATFORM_FLAVOR_fvp) 55 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE); 56 #endif 57 #if defined(PLATFORM_FLAVOR_qemu_virt) 58 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_COHERENT_SIZE); 59 #endif 60 #ifdef DRAM0_BASE 61 register_ddr(DRAM0_BASE, DRAM0_SIZE); 62 #endif 63 #ifdef DRAM1_BASE 64 register_ddr(DRAM1_BASE, DRAM1_SIZE); 65 #endif 66 67 const struct thread_handlers *generic_boot_get_handlers(void) 68 { 69 return &handlers; 70 } 71 72 #ifdef GIC_BASE 73 74 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 75 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 76 77 void main_init_gic(void) 78 { 79 vaddr_t gicc_base; 80 vaddr_t gicd_base; 81 82 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 83 MEM_AREA_IO_SEC); 84 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 85 MEM_AREA_IO_SEC); 86 if (!gicc_base || !gicd_base) 87 panic(); 88 89 #if defined(CFG_WITH_ARM_TRUSTED_FW) 90 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 91 gic_init_base_addr(&gic_data, gicc_base, gicd_base); 92 #else 93 /* Initialize GIC */ 94 gic_init(&gic_data, gicc_base, gicd_base); 95 #endif 96 itr_init(&gic_data.chip); 97 } 98 99 #if !defined(CFG_WITH_ARM_TRUSTED_FW) 100 void main_secondary_init_gic(void) 101 { 102 gic_cpu_init(&gic_data); 103 } 104 #endif 105 106 #endif 107 108 static void main_fiq(void) 109 { 110 gic_it_handle(&gic_data); 111 } 112 113 void console_init(void) 114 { 115 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 116 CONSOLE_BAUDRATE); 117 register_serial_console(&console_data.chip); 118 } 119 120 #if defined(IT_CONSOLE_UART) && \ 121 !(defined(CFG_WITH_ARM_TRUSTED_FW) && defined(CFG_ARM_GICV3)) 122 /* 123 * This cannot be enabled with TF-A and GICv3 because TF-A then need to 124 * assign the interrupt number of the UART to OP-TEE (S-EL1). Currently 125 * there's no way of TF-A to know which interrupts that OP-TEE will serve. 126 * If TF-A doesn't assign the interrupt we're enabling below to OP-TEE it 127 * will hang in EL3 since the interrupt will just be delivered again and 128 * again. 129 */ 130 static enum itr_return console_itr_cb(struct itr_handler *h __unused) 131 { 132 struct serial_chip *cons = &console_data.chip; 133 134 while (cons->ops->have_rx_data(cons)) { 135 int ch __maybe_unused = cons->ops->getchar(cons); 136 137 DMSG("cpu %zu: got 0x%x", get_core_pos(), ch); 138 } 139 return ITRR_HANDLED; 140 } 141 142 static struct itr_handler console_itr = { 143 .it = IT_CONSOLE_UART, 144 .flags = ITRF_TRIGGER_LEVEL, 145 .handler = console_itr_cb, 146 }; 147 KEEP_PAGER(console_itr); 148 149 static TEE_Result init_console_itr(void) 150 { 151 itr_add(&console_itr); 152 itr_enable(IT_CONSOLE_UART); 153 return TEE_SUCCESS; 154 } 155 driver_init(init_console_itr); 156 #endif 157 158 #ifdef CFG_TZC400 159 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC400_BASE, TZC400_REG_SIZE); 160 161 static TEE_Result init_tzc400(void) 162 { 163 void *va; 164 165 DMSG("Initializing TZC400"); 166 167 va = phys_to_virt(TZC400_BASE, MEM_AREA_IO_SEC); 168 if (!va) { 169 EMSG("TZC400 not mapped"); 170 panic(); 171 } 172 173 tzc_init((vaddr_t)va); 174 tzc_dump_state(); 175 176 return TEE_SUCCESS; 177 } 178 179 service_init(init_tzc400); 180 #endif /*CFG_TZC400*/ 181 182 #if defined(PLATFORM_FLAVOR_qemu_virt) 183 static void release_secondary_early_hpen(size_t pos) 184 { 185 struct mailbox { 186 uint64_t ep; 187 uint64_t hpen[]; 188 } *mailbox; 189 190 if (cpu_mmu_enabled()) 191 mailbox = phys_to_virt(SECRAM_BASE, MEM_AREA_IO_SEC); 192 else 193 mailbox = (void *)SECRAM_BASE; 194 195 if (!mailbox) 196 panic(); 197 198 mailbox->ep = TEE_LOAD_ADDR; 199 dsb_ishst(); 200 mailbox->hpen[pos] = 1; 201 dsb_ishst(); 202 sev(); 203 } 204 205 int psci_cpu_on(uint32_t core_id, uint32_t entry, uint32_t context_id) 206 { 207 size_t pos = get_core_pos_mpidr(core_id); 208 static bool core_is_released[CFG_TEE_CORE_NB_CORE]; 209 210 if (!pos || pos >= CFG_TEE_CORE_NB_CORE) 211 return PSCI_RET_INVALID_PARAMETERS; 212 213 DMSG("core pos: %zu: ns_entry %#" PRIx32, pos, entry); 214 215 if (core_is_released[pos]) { 216 EMSG("core %zu already released", pos); 217 return PSCI_RET_DENIED; 218 } 219 core_is_released[pos] = true; 220 221 generic_boot_set_core_ns_entry(pos, entry, context_id); 222 release_secondary_early_hpen(pos); 223 224 return PSCI_RET_SUCCESS; 225 } 226 #endif /*PLATFORM_FLAVOR_qemu_virt*/ 227