xref: /optee_os/core/arch/arm/plat-synquacer/main.c (revision 2dd2ca5f39e6dd144a8be81f5e00badf79d362fe)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (c) 2018, Linaro Limited
4  */
5 
6 #include <arm.h>
7 #include <console.h>
8 #include <drivers/gic.h>
9 #include <drivers/pl011.h>
10 #include <io.h>
11 #include <kernel/generic_boot.h>
12 #include <kernel/misc.h>
13 #include <kernel/panic.h>
14 #include <kernel/pm_stubs.h>
15 #include <kernel/thread.h>
16 #include <kernel/timer.h>
17 #include <mm/core_memprot.h>
18 #include <platform_config.h>
19 #include <sm/optee_smc.h>
20 #include <tee/entry_fast.h>
21 #include <tee/entry_std.h>
22 #include <rng_pta.h>
23 
24 static void main_fiq(void);
25 
26 static const struct thread_handlers handlers = {
27 	.fast_smc = tee_entry_fast,
28 	.nintr = main_fiq,
29 	.cpu_on = cpu_on_handler,
30 	.cpu_off = pm_do_nothing,
31 	.cpu_suspend = pm_do_nothing,
32 	.cpu_resume = pm_do_nothing,
33 	.system_off = pm_do_nothing,
34 	.system_reset = pm_do_nothing,
35 };
36 
37 static struct gic_data gic_data;
38 static struct pl011_data console_data;
39 
40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
41 			CORE_MMU_PGDIR_SIZE);
42 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, THERMAL_SENSOR_BASE,
44 			CORE_MMU_PGDIR_SIZE);
45 
46 const struct thread_handlers *generic_boot_get_handlers(void)
47 {
48 	return &handlers;
49 }
50 
51 static void main_fiq(void)
52 {
53 	gic_it_handle(&gic_data);
54 }
55 
56 void console_init(void)
57 {
58 	pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
59 		   CONSOLE_BAUDRATE);
60 	register_serial_console(&console_data.chip);
61 }
62 
63 void main_init_gic(void)
64 {
65 	vaddr_t gicd_base;
66 
67 	gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET,
68 					  MEM_AREA_IO_SEC);
69 
70 	if (!gicd_base)
71 		panic();
72 
73 	/* On ARMv8-A, GIC configuration is initialized in TF-A */
74 	gic_init_base_addr(&gic_data, 0, gicd_base);
75 
76 	itr_init(&gic_data.chip);
77 }
78 
79 static enum itr_return timer_itr_cb(struct itr_handler *h __unused)
80 {
81 	/* Reset timer for next FIQ */
82 	generic_timer_handler(TIMER_PERIOD_MS);
83 
84 	/* Collect entropy on each timer FIQ */
85 	rng_collect_entropy();
86 
87 	return ITRR_HANDLED;
88 }
89 
90 static struct itr_handler timer_itr = {
91 	.it = IT_SEC_TIMER,
92 	.flags = ITRF_TRIGGER_LEVEL,
93 	.handler = timer_itr_cb,
94 };
95 
96 static TEE_Result init_timer_itr(void)
97 {
98 	itr_add(&timer_itr);
99 	itr_enable(IT_SEC_TIMER);
100 
101 	/* Enable timer FIQ to fetch entropy required during boot */
102 	generic_timer_start(TIMER_PERIOD_MS);
103 
104 	return TEE_SUCCESS;
105 }
106 driver_init(init_timer_itr);
107