1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2018 NXP 4 * Copyright (C) 2015 Freescale Semiconductor, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <platform_config.h> 31 32 #include <arm.h> 33 #include <console.h> 34 #include <drivers/gic.h> 35 #ifdef CFG_PL011 36 #include <drivers/pl011.h> 37 #else 38 #include <drivers/ns16550.h> 39 #endif 40 #include <io.h> 41 #include <kernel/generic_boot.h> 42 #include <kernel/misc.h> 43 #include <kernel/panic.h> 44 #include <kernel/pm_stubs.h> 45 #include <kernel/thread.h> 46 #include <kernel/tz_ssvce_def.h> 47 #include <mm/core_memprot.h> 48 #include <sm/optee_smc.h> 49 #include <tee/entry_fast.h> 50 #include <tee/entry_std.h> 51 #include <kernel/tee_common_otp.h> 52 #include <mm/core_mmu.h> 53 54 static void main_fiq(void); 55 56 static const struct thread_handlers handlers = { 57 .nintr = main_fiq, 58 #if defined(CFG_WITH_ARM_TRUSTED_FW) 59 .cpu_on = cpu_on_handler, 60 .cpu_off = pm_do_nothing, 61 .cpu_suspend = pm_do_nothing, 62 .cpu_resume = pm_do_nothing, 63 .system_off = pm_do_nothing, 64 .system_reset = pm_do_nothing, 65 #else 66 .cpu_on = pm_panic, 67 .cpu_off = pm_panic, 68 .cpu_suspend = pm_panic, 69 .cpu_resume = pm_panic, 70 .system_off = pm_panic, 71 .system_reset = pm_panic, 72 #endif 73 }; 74 75 static struct gic_data gic_data; 76 #ifdef CFG_PL011 77 static struct pl011_data console_data; 78 #else 79 static struct ns16550_data console_data; 80 #endif 81 82 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 83 CORE_MMU_PGDIR_SIZE); 84 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 85 86 const struct thread_handlers *generic_boot_get_handlers(void) 87 { 88 return &handlers; 89 } 90 91 static void main_fiq(void) 92 { 93 panic(); 94 } 95 96 #ifdef CFG_ARM32_core 97 void plat_cpu_reset_late(void) 98 { 99 vaddr_t addr; 100 101 if (!get_core_pos()) { 102 #if defined(CFG_BOOT_SECONDARY_REQUEST) 103 /* set secondary entry address */ 104 io_write32(DCFG_BASE + DCFG_SCRATCHRW1, 105 __compiler_bswap32(TEE_LOAD_ADDR)); 106 107 /* release secondary cores */ 108 io_write32(DCFG_BASE + DCFG_CCSR_BRR /* cpu1 */, 109 __compiler_bswap32(0x1 << 1)); 110 dsb(); 111 sev(); 112 #endif 113 114 /* configure CSU */ 115 116 /* first grant all peripherals */ 117 for (addr = CSU_BASE + CSU_CSL_START; 118 addr != CSU_BASE + CSU_CSL_END; 119 addr += 4) 120 io_write32(addr, __compiler_bswap32(CSU_ACCESS_ALL)); 121 122 /* restrict key preipherals from NS */ 123 io_write32(CSU_BASE + CSU_CSL30, 124 __compiler_bswap32(CSU_ACCESS_SEC_ONLY)); 125 io_write32(CSU_BASE + CSU_CSL37, 126 __compiler_bswap32(CSU_ACCESS_SEC_ONLY)); 127 128 /* lock the settings */ 129 for (addr = CSU_BASE + CSU_CSL_START; 130 addr != CSU_BASE + CSU_CSL_END; 131 addr += 4) 132 io_setbits32(addr, 133 __compiler_bswap32(CSU_SETTING_LOCK)); 134 } 135 } 136 #endif 137 138 void console_init(void) 139 { 140 #ifdef CFG_PL011 141 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 142 CONSOLE_BAUDRATE); 143 #else 144 ns16550_init(&console_data, CONSOLE_UART_BASE); 145 #endif 146 register_serial_console(&console_data.chip); 147 } 148 149 void main_init_gic(void) 150 { 151 vaddr_t gicc_base; 152 vaddr_t gicd_base; 153 154 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 155 MEM_AREA_IO_SEC); 156 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 157 MEM_AREA_IO_SEC); 158 159 if (!gicc_base || !gicd_base) 160 panic(); 161 162 /* Initialize GIC */ 163 gic_init(&gic_data, gicc_base, gicd_base); 164 itr_init(&gic_data.chip); 165 } 166 167 void main_secondary_init_gic(void) 168 { 169 gic_cpu_init(&gic_data); 170 } 171 172 #ifdef CFG_HW_UNQ_KEY_REQUEST 173 174 #include <types_ext.h> 175 int get_hw_unique_key(uint64_t smc_func_id, uint64_t in_key, uint64_t size); 176 177 /* 178 * Issued when requesting to Secure Storage Key for secure storage. 179 * 180 * SiP Service Calls 181 * 182 * Register usage: 183 * r0/x0 SMC Function ID, OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY 184 */ 185 #define OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY 0xFF14 186 #define OPTEE_SMC_FAST_CALL_SIP_LS_HW_UNQ_KEY \ 187 OPTEE_SMC_CALL_VAL(OPTEE_SMC_32, OPTEE_SMC_FAST_CALL, \ 188 OPTEE_SMC_OWNER_SIP, \ 189 OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY) 190 191 TEE_Result tee_otp_get_hw_unique_key(struct tee_hw_unique_key *hwkey) 192 { 193 TEE_Result res; 194 int ret = 0; 195 uint8_t hw_unq_key[sizeof(hwkey->data)] __aligned(64); 196 197 ret = get_hw_unique_key(OPTEE_SMC_FAST_CALL_SIP_LS_HW_UNQ_KEY, 198 virt_to_phys(hw_unq_key), sizeof(hwkey->data)); 199 200 if (ret < 0) { 201 EMSG("\nH/W Unique key is not fetched from the platform."); 202 res = TEE_ERROR_SECURITY; 203 } else { 204 memcpy(&hwkey->data[0], hw_unq_key, sizeof(hwkey->data)); 205 res = TEE_SUCCESS; 206 } 207 208 return res; 209 } 210 #endif 211