| 26c22a5e | 23-Jul-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: sanity check power state type
This patch sanity checks the power state type before use,
from the platform's PSCI handler.
Verified with TFTF Standard Test Suite.
Change-Id: Icd45faac6c02
Tegra186: sanity check power state type
This patch sanity checks the power state type before use,
from the platform's PSCI handler.
Verified with TFTF Standard Test Suite.
Change-Id: Icd45faac6c023d4ce7f3597b698d01b91a218124
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 36e26375 | 07-Jan-2019 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra: memctrl: cleanup streamid override registers
Streamid override registers are passed to memctrl to program bypass
streamid for all the registers. There is no reason to bypass SMMU
for any of t
Tegra: memctrl: cleanup streamid override registers
Streamid override registers are passed to memctrl to program bypass
streamid for all the registers. There is no reason to bypass SMMU
for any of the client so need to remove register list and do not
set streamid_override_cfg.
Some Tegra186 platforms don't boot due to SDMMC failure so keep SDMMC
bypass as of now. Will revisit once these issues are fixed.
Change-Id: I3f67e2a0e1b53160e2218f3acace7da45532f934
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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| 2139c9c8 | 09-Nov-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: system resume from TZSRAM memory
TZSRAM loses power during System suspend, so the entire contents
are copied to TZDRAM before Sysem Suspend entry. The warmboot code
verifies and restores t
Tegra186: system resume from TZSRAM memory
TZSRAM loses power during System suspend, so the entire contents
are copied to TZDRAM before Sysem Suspend entry. The warmboot code
verifies and restores the contents to TZSRAM during System Resume.
This patch removes the code that sets up CPU vector to point to
TZSRAM during System Resume as a result. The trampoline code can
also be completely removed as a result.
Change-Id: I2830eb1db16efef3dfd96c4e3afc41a307588ca1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 7d74487c | 28-Jun-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: store TZDRAM base/size to scratch registers
This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify in
Tegra186: store TZDRAM base/size to scratch registers
This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify integrity of the TZDRAM aperture.
Change-Id: Ic70914cb958249f06cb58025a24d13734a85e16e
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 4eed9c84 | 19-Jul-2018 |
Jeetesh Burman <jburman@nvidia.com> |
Tegra186: add SE support to generate SHA256 of TZRAM
The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
s
Tegra186: add SE support to generate SHA256 of TZRAM
The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.
This patch adds driver for the SE engine, with APIs to calculate the hash
and store SE SHA256 hash-result to PMC scratch registers.
Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
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