1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SMMU_H 9 #define SMMU_H 10 11 #include <lib/mmio.h> 12 13 #include <memctrl_v2.h> 14 #include <tegra_def.h> 15 16 #define SMMU_CBn_ACTLR (0x4U) 17 18 /******************************************************************************* 19 * SMMU Global Secure Aux. Configuration Register 20 ******************************************************************************/ 21 #define SMMU_GSR0_SECURE_ACR 0x10U 22 #define SMMU_GNSR_ACR (SMMU_GSR0_SECURE_ACR + 0x400U) 23 #define SMMU_GSR0_PGSIZE_SHIFT 16U 24 #define SMMU_GSR0_PGSIZE_4K (0U << SMMU_GSR0_PGSIZE_SHIFT) 25 #define SMMU_GSR0_PGSIZE_64K (1U << SMMU_GSR0_PGSIZE_SHIFT) 26 #define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1U << 26) 27 28 /******************************************************************************* 29 * SMMU Global Aux. Control Register 30 ******************************************************************************/ 31 #define SMMU_CBn_ACTLR_CPRE_BIT (1ULL << 1U) 32 33 void tegra_smmu_init(void); 34 uint32_t plat_get_num_smmu_devices(void); 35 36 #endif /* SMMU_H */ 37