1/* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8#include <arch.h> 9#include <asm_macros.S> 10#include <common/bl_common.h> 11#include <memctrl_v2.h> 12#include <plat/common/common_def.h> 13#include <tegra_def.h> 14 15#define TEGRA186_MC_CTX_SIZE 0x93 16 17 .globl tegra186_cpu_reset_handler 18 19/* CPU reset handler routine */ 20func tegra186_cpu_reset_handler _align=4 21 /* prepare to relocate to TZSRAM */ 22 mov x0, #BL31_BASE 23 adr x1, __tegra186_cpu_reset_handler_end 24 adr x2, __tegra186_cpu_reset_handler_data 25 ldr x2, [x2, #8] 26 27 /* memcpy16 */ 28m_loop16: 29 cmp x2, #16 30 b.lt m_loop1 31 ldp x3, x4, [x1], #16 32 stp x3, x4, [x0], #16 33 sub x2, x2, #16 34 b m_loop16 35 /* copy byte per byte */ 36m_loop1: 37 cbz x2, boot_cpu 38 ldrb w3, [x1], #1 39 strb w3, [x0], #1 40 subs x2, x2, #1 41 b.ne m_loop1 42 43boot_cpu: 44 adr x0, __tegra186_cpu_reset_handler_data 45 ldr x0, [x0] 46 br x0 47endfunc tegra186_cpu_reset_handler 48 49 /* 50 * Tegra186 reset data (offset 0x0 - 0x430) 51 * 52 * 0x000: secure world's entrypoint 53 * 0x008: BL31 size (RO + RW) 54 * 0x00C: MC context start 55 * 0x42C: MC context end 56 */ 57 58 .align 4 59 .type __tegra186_cpu_reset_handler_data, %object 60 .globl __tegra186_cpu_reset_handler_data 61__tegra186_cpu_reset_handler_data: 62 .quad tegra_secure_entrypoint 63 .quad __BL31_END__ - BL31_BASE 64 65 .globl __tegra186_system_suspend_state 66__tegra186_system_suspend_state: 67 .quad 0 68 69 .align 4 70 .globl __tegra186_mc_context 71__tegra186_mc_context: 72 .rept TEGRA186_MC_CTX_SIZE 73 .quad 0 74 .endr 75 .size __tegra186_cpu_reset_handler_data, \ 76 . - __tegra186_cpu_reset_handler_data 77 78 .align 4 79 .globl __tegra186_cpu_reset_handler_end 80__tegra186_cpu_reset_handler_end: 81 82 .globl tegra186_get_cpu_reset_handler_size 83 .globl tegra186_get_cpu_reset_handler_base 84 .globl tegra186_get_mc_ctx_offset 85 86/* return size of the CPU reset handler */ 87func tegra186_get_cpu_reset_handler_size 88 adr x0, __tegra186_cpu_reset_handler_end 89 adr x1, tegra186_cpu_reset_handler 90 sub x0, x0, x1 91 ret 92endfunc tegra186_get_cpu_reset_handler_size 93 94/* return the start address of the CPU reset handler */ 95func tegra186_get_cpu_reset_handler_base 96 adr x0, tegra186_cpu_reset_handler 97 ret 98endfunc tegra186_get_cpu_reset_handler_base 99 100/* return the size of the MC context */ 101func tegra186_get_mc_ctx_offset 102 adr x0, __tegra186_mc_context 103 adr x1, tegra186_cpu_reset_handler 104 sub x0, x0, x1 105 ret 106endfunc tegra186_get_mc_ctx_offset 107