1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl31/bl31.h> 10 #include <common/bl_common.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/console.h> 13 #include <context.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <cortex_a57.h> 16 #include <common/debug.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <bl31/interrupt_mgmt.h> 21 #include <mce.h> 22 #include <mce_private.h> 23 #include <plat/common/platform.h> 24 #include <spe.h> 25 #include <tegra_def.h> 26 #include <tegra_mc_def.h> 27 #include <tegra_platform.h> 28 #include <tegra_private.h> 29 #include <lib/xlat_tables/xlat_tables_v2.h> 30 31 /* ID for spe-console */ 32 #define TEGRA_CONSOLE_SPE_ID 0xFE 33 34 /******************************************************************************* 35 * Structure to store the SCR addresses and its expected settings. 36 ******************************************************************************* 37 */ 38 typedef struct { 39 uint32_t scr_addr; 40 uint32_t scr_val; 41 } scr_settings_t; 42 43 static const scr_settings_t t194_scr_settings[] = { 44 { SCRATCH_RSV68_SCR, SCRATCH_RSV68_SCR_VAL }, 45 { SCRATCH_RSV71_SCR, SCRATCH_RSV71_SCR_VAL }, 46 { SCRATCH_RSV72_SCR, SCRATCH_RSV72_SCR_VAL }, 47 { SCRATCH_RSV75_SCR, SCRATCH_RSV75_SCR_VAL }, 48 { SCRATCH_RSV81_SCR, SCRATCH_RSV81_SCR_VAL }, 49 { SCRATCH_RSV97_SCR, SCRATCH_RSV97_SCR_VAL }, 50 { SCRATCH_RSV99_SCR, SCRATCH_RSV99_SCR_VAL }, 51 { SCRATCH_RSV109_SCR, SCRATCH_RSV109_SCR_VAL }, 52 { MISCREG_SCR_SCRTZWELCK, MISCREG_SCR_SCRTZWELCK_VAL } 53 }; 54 55 /******************************************************************************* 56 * The Tegra power domain tree has a single system level power domain i.e. a 57 * single root node. The first entry in the power domain descriptor specifies 58 * the number of power domains at the highest power level. 59 ******************************************************************************* 60 */ 61 static const uint8_t tegra_power_domain_tree_desc[] = { 62 /* No of root nodes */ 63 1, 64 /* No of clusters */ 65 PLATFORM_CLUSTER_COUNT, 66 /* No of CPU cores - cluster0 */ 67 PLATFORM_MAX_CPUS_PER_CLUSTER, 68 /* No of CPU cores - cluster1 */ 69 PLATFORM_MAX_CPUS_PER_CLUSTER, 70 /* No of CPU cores - cluster2 */ 71 PLATFORM_MAX_CPUS_PER_CLUSTER, 72 /* No of CPU cores - cluster3 */ 73 PLATFORM_MAX_CPUS_PER_CLUSTER 74 }; 75 76 /******************************************************************************* 77 * This function returns the Tegra default topology tree information. 78 ******************************************************************************/ 79 const uint8_t *plat_get_power_domain_tree_desc(void) 80 { 81 return tegra_power_domain_tree_desc; 82 } 83 84 /* 85 * Table of regions to map using the MMU. 86 */ 87 static const mmap_region_t tegra_mmap[] = { 88 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */ 89 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 90 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ 91 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 92 MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */ 93 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 94 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */ 95 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 96 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */ 97 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 98 #if !ENABLE_CONSOLE_SPE 99 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ 100 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 101 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ 102 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 103 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ 104 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 105 #endif 106 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */ 107 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 108 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */ 109 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 110 MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */ 111 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 112 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */ 113 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 114 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */ 115 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 116 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */ 117 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 118 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */ 119 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 120 #if ENABLE_CONSOLE_SPE 121 MAP_REGION_FLAT(TEGRA_CONSOLE_SPE_BASE, 0x1000U, /* 4KB */ 122 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 123 #endif 124 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, TEGRA_TMRUS_SIZE, /* 4KB */ 125 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 126 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */ 127 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 128 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x800000U, /* 8MB */ 129 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 130 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x800000U, /* 8MB */ 131 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 132 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x800000U, /* 8MB */ 133 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 134 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */ 135 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 136 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ 137 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 138 {0} 139 }; 140 141 /******************************************************************************* 142 * Set up the pagetables as per the platform memory map & initialize the MMU 143 ******************************************************************************/ 144 const mmap_region_t *plat_get_mmio_map(void) 145 { 146 /* MMIO space */ 147 return tegra_mmap; 148 } 149 150 /******************************************************************************* 151 * Handler to get the System Counter Frequency 152 ******************************************************************************/ 153 uint32_t plat_get_syscnt_freq2(void) 154 { 155 return 31250000; 156 } 157 158 #if !ENABLE_CONSOLE_SPE 159 /******************************************************************************* 160 * Maximum supported UART controllers 161 ******************************************************************************/ 162 #define TEGRA194_MAX_UART_PORTS 7 163 164 /******************************************************************************* 165 * This variable holds the UART port base addresses 166 ******************************************************************************/ 167 static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = { 168 0, /* undefined - treated as an error case */ 169 TEGRA_UARTA_BASE, 170 TEGRA_UARTB_BASE, 171 TEGRA_UARTC_BASE, 172 TEGRA_UARTD_BASE, 173 TEGRA_UARTE_BASE, 174 TEGRA_UARTF_BASE, 175 TEGRA_UARTG_BASE 176 }; 177 #endif 178 179 /******************************************************************************* 180 * Enable console corresponding to the console ID 181 ******************************************************************************/ 182 void plat_enable_console(int32_t id) 183 { 184 uint32_t console_clock = 0U; 185 186 #if ENABLE_CONSOLE_SPE 187 static console_t spe_console; 188 189 if (id == TEGRA_CONSOLE_SPE_ID) { 190 (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE, 191 console_clock, 192 TEGRA_CONSOLE_BAUDRATE, 193 &spe_console); 194 console_set_scope(&spe_console, CONSOLE_FLAG_BOOT | 195 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 196 } 197 #else 198 static console_t uart_console; 199 200 if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) { 201 /* 202 * Reference clock used by the FPGAs is a lot slower. 203 */ 204 if (tegra_platform_is_fpga()) { 205 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; 206 } else { 207 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; 208 } 209 210 (void)console_16550_register(tegra194_uart_addresses[id], 211 console_clock, 212 TEGRA_CONSOLE_BAUDRATE, 213 &uart_console); 214 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT | 215 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 216 } 217 #endif 218 } 219 220 /******************************************************************************* 221 * Verify SCR settings 222 ******************************************************************************/ 223 static inline bool tegra194_is_scr_valid(void) 224 { 225 uint32_t scr_val; 226 bool ret = true; 227 228 for (uint8_t i = 0U; i < ARRAY_SIZE(t194_scr_settings); i++) { 229 scr_val = mmio_read_32((uintptr_t)t194_scr_settings[i].scr_addr); 230 if (scr_val != t194_scr_settings[i].scr_val) { 231 ERROR("Mismatch at SCR addr = 0x%x\n", t194_scr_settings[i].scr_addr); 232 ret = false; 233 } 234 } 235 return ret; 236 } 237 238 /******************************************************************************* 239 * Handler for early platform setup 240 ******************************************************************************/ 241 void plat_early_platform_setup(void) 242 { 243 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 244 uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step; 245 uint64_t actlr_elx; 246 247 /* Verify chip id is t194 */ 248 assert(tegra_chipid_is_t194()); 249 250 /* Verify SCR settings */ 251 if (tegra_platform_is_silicon()) { 252 assert(tegra194_is_scr_valid()); 253 } 254 255 /* sanity check MCE firmware compatibility */ 256 mce_verify_firmware_version(); 257 258 #if RAS_EXTENSION 259 /* Enable Uncorrectable RAS error */ 260 tegra194_ras_enable(); 261 #endif 262 263 /* 264 * Program XUSB STREAMIDs 265 * ====================== 266 * T19x XUSB has support for XUSB virtualization. It will have one 267 * physical function (PF) and four Virtual function (VF) 268 * 269 * There were below two SIDs for XUSB until T186. 270 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU 271 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU 272 * 273 * We have below four new SIDs added for VF(s) 274 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU 275 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU 276 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU 277 * 6) #define TEGRA_SID_XUSB_VF3 0x60U 278 * 279 * When virtualization is enabled then we have to disable SID override 280 * and program above SIDs in below newly added SID registers in XUSB 281 * PADCTL MMIO space. These registers are TZ protected and so need to 282 * be done in ATF. 283 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 284 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 285 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 286 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 287 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 288 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 289 * 290 * This change disables SID override and programs XUSB SIDs in 291 * above registers to support both virtualization and 292 * non-virtualization platforms 293 */ 294 if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { 295 296 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 297 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); 298 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE + 299 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_HOST); 300 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 301 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); 302 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE + 303 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0) == TEGRA_SID_XUSB_VF0); 304 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 305 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); 306 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE + 307 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1) == TEGRA_SID_XUSB_VF1); 308 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 309 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); 310 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE + 311 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2) == TEGRA_SID_XUSB_VF2); 312 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 313 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); 314 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE + 315 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3) == TEGRA_SID_XUSB_VF3); 316 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 317 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); 318 assert(mmio_read_32(TEGRA_XUSB_PADCTL_BASE + 319 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0) == TEGRA_SID_XUSB_DEV); 320 } 321 322 /* 323 * Enable dual execution optimized translations for all ELx. 324 */ 325 if (enable_ccplex_lock_step != 0U) { 326 actlr_elx = read_actlr_el3(); 327 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3; 328 write_actlr_el3(actlr_elx); 329 /* check if the bit is actually set */ 330 assert((read_actlr_el3() & DENVER_CPU_ENABLE_DUAL_EXEC_EL3) != 0ULL); 331 332 actlr_elx = read_actlr_el2(); 333 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2; 334 write_actlr_el2(actlr_elx); 335 /* check if the bit is actually set */ 336 assert((read_actlr_el2() & DENVER_CPU_ENABLE_DUAL_EXEC_EL2) != 0ULL); 337 338 actlr_elx = read_actlr_el1(); 339 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1; 340 write_actlr_el1(actlr_elx); 341 /* check if the bit is actually set */ 342 assert((read_actlr_el1() & DENVER_CPU_ENABLE_DUAL_EXEC_EL1) != 0ULL); 343 } 344 } 345 346 /* Secure IRQs for Tegra194 */ 347 static const interrupt_prop_t tegra194_interrupt_props[] = { 348 INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI, 349 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 350 INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO, 351 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 352 }; 353 354 /******************************************************************************* 355 * Initialize the GIC and SGIs 356 ******************************************************************************/ 357 void plat_gic_setup(void) 358 { 359 tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props)); 360 tegra_gic_init(); 361 362 /* 363 * Initialize the FIQ handler 364 */ 365 tegra_fiq_handler_setup(); 366 } 367 368 /******************************************************************************* 369 * Return pointer to the BL31 params from previous bootloader 370 ******************************************************************************/ 371 struct tegra_bl31_params *plat_get_bl31_params(void) 372 { 373 uint64_t val; 374 375 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) & 376 SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT; 377 val <<= 32; 378 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR); 379 380 return (struct tegra_bl31_params *)(uintptr_t)val; 381 } 382 383 /******************************************************************************* 384 * Return pointer to the BL31 platform params from previous bootloader 385 ******************************************************************************/ 386 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 387 { 388 uint64_t val; 389 390 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) & 391 SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT; 392 val <<= 32; 393 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR); 394 395 return (plat_params_from_bl2_t *)(uintptr_t)val; 396 } 397 398 /******************************************************************************* 399 * Handler for late platform setup 400 ******************************************************************************/ 401 void plat_late_platform_setup(void) 402 { 403 #if ENABLE_STRICT_CHECKING_MODE 404 /* 405 * Enable strict checking after programming the GSC for 406 * enabling TZSRAM and TZDRAM 407 */ 408 mce_enable_strict_checking(); 409 mce_verify_strict_checking(); 410 #endif 411 } 412 413 /******************************************************************************* 414 * Handler to indicate support for System Suspend 415 ******************************************************************************/ 416 bool plat_supports_system_suspend(void) 417 { 418 return true; 419 } 420