1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 16 #include <smmu.h> 17 #include <tegra_private.h> 18 19 extern void memcpy16(void *dest, const void *src, unsigned int length); 20 21 #define SMMU_NUM_CONTEXTS 64U 22 #define SMMU_CONTEXT_BANK_MAX_IDX 64U 23 24 /* 25 * Init SMMU during boot or "System Suspend" exit 26 */ 27 void tegra_smmu_init(void) 28 { 29 uint32_t val, cb_idx, smmu_id, ctx_base; 30 uint32_t smmu_counter = plat_get_num_smmu_devices(); 31 32 for (smmu_id = 0U; smmu_id < smmu_counter; smmu_id++) { 33 /* Program the SMMU pagesize and reset CACHE_LOCK bit */ 34 val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); 35 val |= SMMU_GSR0_PGSIZE_64K; 36 val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; 37 tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); 38 39 /* reset CACHE LOCK bit for NS Aux. Config. Register */ 40 val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); 41 val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; 42 tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); 43 44 /* disable TCU prefetch for all contexts */ 45 ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) 46 + SMMU_CBn_ACTLR; 47 for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) { 48 val = tegra_smmu_read_32(smmu_id, 49 ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx)); 50 val &= (uint32_t)~SMMU_CBn_ACTLR_CPRE_BIT; 51 tegra_smmu_write_32(smmu_id, ctx_base + 52 (SMMU_GSR0_PGSIZE_64K * cb_idx), val); 53 } 54 55 /* set CACHE LOCK bit for NS Aux. Config. Register */ 56 val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); 57 val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT; 58 tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); 59 60 /* set CACHE LOCK bit for S Aux. Config. Register */ 61 val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); 62 val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT; 63 tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); 64 } 65 } 66