1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <lib/mmio.h> 13 14 #include <mce.h> 15 #include <tegra186_private.h> 16 #include <tegra_def.h> 17 #include <tegra_private.h> 18 19 #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U 20 #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU 21 22 #define CPU_RESET_MODE_AA64 1U 23 24 extern void memcpy16(void *dest, const void *src, unsigned int length); 25 26 /******************************************************************************* 27 * Setup secondary CPU vectors 28 ******************************************************************************/ 29 void plat_secondary_setup(void) 30 { 31 uint32_t addr_low, addr_high; 32 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 33 uint64_t cpu_reset_handler_base, cpu_reset_handler_size; 34 35 INFO("Setting up secondary CPU boot\n"); 36 37 /* 38 * The BL31 code resides in the TZSRAM which loses state 39 * when we enter System Suspend. Copy the wakeup trampoline 40 * code to TZDRAM to help us exit from System Suspend. 41 */ 42 cpu_reset_handler_base = tegra186_get_cpu_reset_handler_base(); 43 cpu_reset_handler_size = tegra186_get_cpu_reset_handler_size(); 44 (void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base, 45 (const void *)(uintptr_t)cpu_reset_handler_base, 46 cpu_reset_handler_size); 47 48 /* TZDRAM base will be used as the "resume" address */ 49 addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; 50 addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); 51 52 /* save reset vector to be used during SYSTEM_SUSPEND exit */ 53 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, 54 addr_low); 55 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, 56 addr_high); 57 } 58