1 /* 2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/bl_common.h> 9 #include <mce.h> 10 #include <memctrl_v2.h> 11 #include <tegra_mc_def.h> 12 #include <tegra_platform.h> 13 #include <tegra_private.h> 14 15 /******************************************************************************* 16 * Array to hold MC context for Tegra194 17 ******************************************************************************/ 18 static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = { 19 _START_OF_TABLE_, 20 mc_smmu_bypass_cfg, /* TBU settings */ 21 _END_OF_TABLE_, 22 }; 23 24 /******************************************************************************* 25 * Handler to return the pointer to the MC's context struct 26 ******************************************************************************/ 27 mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void) 28 { 29 /* index of _END_OF_TABLE_ */ 30 tegra194_mc_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_mc_context) - 1U; 31 32 return tegra194_mc_context; 33 } 34 35 /******************************************************************************* 36 * Handler to restore platform specific settings to the memory controller 37 ******************************************************************************/ 38 void plat_memctrl_restore(void) 39 { 40 UNUSED_FUNC_NOP(); /* do nothing */ 41 } 42 43 /******************************************************************************* 44 * Handler to program platform specific settings to the memory controller 45 ******************************************************************************/ 46 void plat_memctrl_setup(void) 47 { 48 UNUSED_FUNC_NOP(); /* do nothing */ 49 } 50 51 /******************************************************************************* 52 * Handler to program the scratch registers with TZDRAM settings for the 53 * resume firmware 54 ******************************************************************************/ 55 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) 56 { 57 uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); 58 uint32_t phys_base_lo = (uint32_t)phys_base & 0xFFF00000; 59 uint32_t phys_base_hi = (uint32_t)(phys_base >> 32); 60 61 /* 62 * Check TZDRAM carveout register access status. Setup TZDRAM fence 63 * only if access is enabled. 64 */ 65 if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) == 66 SECURITY_CFG_WRITE_ACCESS_ENABLE) { 67 68 /* 69 * Setup the Memory controller to allow only secure accesses to 70 * the TZDRAM carveout 71 */ 72 INFO("Configuring TrustZone DRAM Memory Carveout\n"); 73 74 tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base_lo); 75 tegra_mc_write_32(MC_SECURITY_CFG3_0, phys_base_hi); 76 tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); 77 78 /* 79 * MCE propagates the security configuration values across the 80 * CCPLEX. 81 */ 82 (void)mce_update_gsc_tzdram(); 83 } 84 } 85